World's 1st FPGA/CPLD Portal

AMRISH J PATEL
+ 919663367036, amrish.j.patel@gmail.com

Front End Design Engineer

Engineering professional having progressive experience in developing FPGA designs for the WiMax systems and other embedded systems.

Extensive knowledge of design flow, design techniques, tools, languages and principles involved in developing FPGA designs for complex embedded systems.

5+ years of development experience of Physical layers of the WiMAX 802.16d & e.

PROFESSIONAL EXPERIENCE

Cisco Systems, Bangalore.
Hardware Engineer, BWBU
Sept’08 – Present

Responsibilities at Cisco
Manage all aspects of the FPGA subsystem like
- Designing the subsystem, defining micro-architectures within the subsystem, defining implementation details.
- Define design specifications; prepare design and functional specification documents.
- Come up with unit level test plan, evaluation test plan and integration test plan.

Perform RTL coding. Develop functional simulation environment for unit level testing. Perform evaluation level testing on Evaluation Hardware Board and integration level testing on Target Hardware Board.

Participate in Design, Code and Test Plan peer reviews. Comply with Quality processes and meeting the quality targets set for the project (such as, defect density, code coverage, etc.)

Tata Elxsi Limited, Bangalore.
Senior Engineer, ASIC/FPGA.
Oct’04 – Aug’08

Responsibilities at Tata Elxsi
Leading and managing all aspects of FPGA team.
Conceptualizing and designing FPGA architectures for embedded systems. This includes defining micro-architectures, implementation details, HW/SW interface. Perform RTL coding and standalone testing.
Co-ordinate and work with PHY, MAC and HW team to perform system integration and system testing.

CAREER PROFILE

P4 Project, Bangalore
Hardware Engineer, Sept’08 – Present

P4 WiMAX system is the second generation WiMAX 802.16e / 802.15-2005 compliant macrocell BTS. It’s a tower-top unit compromised of two subsystems, the Antenna Unit (AU) and the Radio Unit (RU). Support for 5 MHz and 10 MHz bandwidth operating modes. Support for 100/1000 BASE-FX Ethernet backhaul and management.
? Worked on PROFEC subsystem. Ethernet MAC IP, Packet processor containing NIOS II and CTC Core are the major processing blocks of this subsystem.
? Design and build the PROFEC SOPC subsystem. Perform RTL Coding. Timing closure.
? Develop test environment for functional simulation. Carry out unit level testing, evaluation level testing and integration level testing.

Florence Project, Italy
Senior FPGA Engineer, Nov’07 – Aug’08.

Florence adheres to WiMax 802.16e standard specifications. The platform includes SRDP board with DSP and PQ3 AMC cards. Base Station MAC is running on PowerQUICC III MPC8548 processor, PHY running on TI DSPs. Similar setup has Mobile station MAC running on PowerQUICC III MPC8548 processor, PHY running on TI DSP's. FPGA running on IFU board does the time domain processing of OFDMA symbols. DSP communicates to FPGA board via 4x SRIO lanes at 3.125 Gbps. FPGA system includes SRIO Xilinx IP core and SRIO Interface. Uplink and downlink IQ buffer management, Up sampling block, Down sampling block, WiMax frame generation and system timing module, ADC & DAC interface and CPU SPI Interface.
? Worked on WIMAX Frame generation module, uplink signal chain and SRIO interface.
? Responsibilities include leading and managing all aspects of FPGA team. Understanding and designing FPGA system, defining micro architecture and implementation details.
? RTL coding and testing of above modules.
? Designing of test simulation environment. Debug environment for run time debugging of FPGA system.
? Co-ordinate and work with DSP, MAC and hardware team to perform system integration and system testing.

Limantour Project, India
Senior FPGA Engineer, April’07 – Sept’07.

Limantour is WiMax 802.16e demonstration platform. The demonstration platform includes Base Station MAC running on PowerQUICC III MPC8548 processor, PHY running on TI DSP’s, and a mobile system simulator running on a PC together with a GUI that controls whole system. FPGA system includes SRIO Interface, CTC (Convolution Turbo Code) Decoder and SRIO CTC Interface. DSP needs forward error correction algorithm. This functionality is implemented in FPGA using turbo decoder IP core (TC1000-Wimax). DSP communicates to turbo decoder IP Core via SRIO interface.
? Worked on SRIO CTC interface and SRIO Xilinx IP core.
? Responsibilities include leading and managing all aspects of FPGA team. Understanding and designing FPGA system, defining micro architecture and implementation details.
? RTL coding, unit testing of above modules, standalone testing and system level testing.

MUSUME Project, UK
FPGA Engineer, Aug’06 – Feb’07.

Musume is next generation personal handy phone system (NG-PHS). NG-PHS as as well as the original PHS is a broadband wireless access system. It’s a cost- effective alternative to conventional 2G and 3G systems. Frequency band from 1 - 3GHz and carrier frequency width of 5 – 20 MHz. Data transmission speed of 20 Mbps or more for both upstream and downstream with OFDMA + TDMA/TDD access technologies. Modulation BPSK – 256 QAM.
? Worked on Downlink Channel – signal chain includes OFDM IFFT Cyclic Prefix, Digital UP Conversion, Timing Acquisition Block to synchronize receiver, Test Vector Player to push dummy frames to downlink and uplink channel.
? Responsibilities include designing, RTL coding and unit level testing of above modules.
? System testing with PHY and MAC running.

WAD Project, India
FPGA Engineer, November’04 – July’06.

WAD is an ISDN to IP gateway for videoconferencing applications. It provides the connectivity for the packet switched IP based video conferencing equipments (H.323 protocol) to the existing/already deployed circuit switched ISDN based video conferencing equipments (H.320 protocol). Up to 68*64K ISDN channels can be simultaneously supported (2 PRI, 4 BRI). Up to 30*64K channels can be bonded in a single call through H.244 Bonding and ISO Bonding. In addition V.35 interface can support calls from 64K to 2M bandwidth. H.221 protocol defines multiplexing audio (G.711, G.722, G.728, G.729), video (H.261, H.263) and low speed data on to the ISDN channels.
? Worked on BRI, PRI and V.35 Interface for H.221 framing and H.221 frame detection modules, H.221 Mux/Demux, V.35 Buffering and buffer management for 64 Kbps to 2 Mbps, ISO13871 Bonding and Delay Equalization.
? Responsibilities include designing and implementing above modules. Unit level testing of above modules as well as standalone testing.

TECHNICAL PROFICIENCIES

Languages : Verilog, VHDL, C, PERL.
EDA Tools : Xilinx ISE, ALTERA QUARTUS, ALTERA SOPC BUILDER, XILINX VIRTEX FPGA’s, ALTERA STRATIX FPGA’s, NIOS II 8.0 IDE, Synplify-Pro, ModelSim, Exemplar LeoSpec.
Allied Tools : Logic Analyzer (Agilent Technologies 1670G), Agilent Technologies Signal Analyzer, Rohde & Schwarz Spectrum Analyzer.
Domain Specific : Rapid IO, Videoconferencing protocol H.221, Interface Standard V.35, PCI, USB.

EDUCATION

Post Graduate Diploma in VLSI Designing, 2004
CDAC-ACTS, Pune.

Bachelor of Engineering (Instrumentation & Control), 2002
South Gujarat University, Gujarat.

PROFESSIONAL ACTIVITIES
? Altera certified professional.
? Worked as a “Customer Care Representative” for world largest auction site “EBAY.COM”.
? Active member of WWF (World Wide Fund for Nature).

REFERENCES
Available on request.