World's 1st FPGA/CPLD Portal

IO Checker is a new and easy to use tool, to verify that an FPGA is connected to the same signal names on the PCB as programmed in the FPGA environment. Additionally it verifies the voltage values connected to the FPGA power and references pins.

Intelligent Verification

IO Checker uses rules (based on regular expressions) to match the signals names in both the FPGA and PCB design environment.
It allows the tool to validate groups of matches although individual signals can still differ. The rules can be generated automatically and be fine-tuned by the designer. The automated approach will often match 80% to 90% of all device pins.

The flexibility of IO Checker allows it to be used in any design flow and does not require any design methodology. The rules generator in combination with the sorted problem view allows engineers to validate a 1000+ pins device in half an hour.

FPGA and PCB support

IO Checker support the majority of devices from Altera (Cyclone, Stratix, Arria) and Xilinx (Virtex5, Virtex4, Spartan3 and Virtex2). Please check the website for detailed device listings. Supported PCB tools include Altium, Cadence (Allegro and Orcad) and Mentor Graphics (DxDesigner, PADS and Veribest).

Availability and Pricing

IO Checker 1.0 is available now. Prices begin at € 750 or US$1,125. IO Checker can be downloaded and evaluated by qualified FPGA and PCB designers.