World's 1st FPGA Portal

There was a large gap existing between standard cell-based design and FPGA, even when FPGA was introduced to overcome the gap. But the design size, design complexity and design performance were limited in FPGA and design per unit cost was high. Structured ASIC introduced to overcome these limitations and it takes advantage of FPGA as well as standard cell-based design. The design task for structured ASIC’s is to map the circuit into a fixed arrangements of known cells. Structured ASICs offer designers a set of devices with specific, customizable metal layers along with predefined metal layers, which can contain the underlying pattern of logic cells, memory, and I/O.
Two main levels of architecture in a structured ASIC, first one is structured elements and other one is array of structured element. Structured elements can be either combinational or sequential function blocks. It can be logical or storage element. The array of structured element may be uniform or non-uniform array style.

Advantage:
- Easier and faster than standard cell-based ASIC,
- Capacity, performance, and power consumption closer to that of a standard cell ASIC,
- Faster design time, reduced NRE costs, and quicker turnaround,
- Therefore, the per-unit cost is reasonable for several hundreds to 100k unit production runs.
Disadvantage:
• Lack of adequate design tools,
– Expensive,
– Altered from traditional ASIC tools.
• These new architectures have not yet been subject to formal evaluation and comparative analysis,
– Tradeoffs between 3-, 4-, and 5-input LUT’s,
– Tradeoffs between sizes of distributed RAM.