PLA - Programmable logic arrays

PLAs became available in 1975 to address the limitations imposed by the PROM architecture, where both planes AND and OR arrays were programmable. Logically, a PLA is a circuit that allows implementing Boolean functions in sum-of-product form. The number of AND functions in the AND array is independent of the number of inputs. Additional ANDs can be formed by simply introducing more rows into the array. Similarly, the number of OR functions in the OR array is independent of both the number of inputs and number of AND functions in the AND array. ORs can be formed by introducing additional columns into the array. Each place in the AND-matrix holds a small diode. Depending on the programming data, this diode is left unconnected, or connected to its input-line and product-line. While the unconnected diode will do nothing, the product-term line will be driven low by the connected diode whenever the corresponding input-line is low. This is the wired-AND operation: a product term will only remain high when none of the (connected!) input-lines is driven low.

Structure of PLA Device

In implementing a combinational circuit with a PLA, a careful investigation must be undertaken in order to reduce the number of distinct product terms, so that the complexity of the circuit may be reduced. Fewer product terms can be achieved by simplifying the Boolean function to a minimum number of terms.

General Architecture of PLA Device
Image Courtesy:

PLA shares single product term across multiple ORs array, so highest logic density is available to the user. The number of fuse count is high in PALs. The main advantage of the PLA structure is that a very compact and space-efficient realization is possible in NMOS technology. Small self-conducting (enhancement-mode) NMOS transistors are used for the pull-up resistors, while a depletion-mode NMOS transistor is placed at each location in the AND- and OR-matrices.

PLA NMOS Technology View

Example: Let us consider multiple functions of A, B, C
F2= A + B + C
F3= not (ABC)
F4= not (A + B + C)
F5= A xor B xor C
F6= A xnor B xnor C
As true and complemented inputs are available, different product term can be produce by AND arrays by simply connected diode on AND plane and finally output will get through OR arrays as shown in figure below.

Logic implimentation on PLA
Image Courtesy:

Facebook  Twitter  Linkedin  Orkut  YouTube      RSS


Check out FPGA related videos

Find Us On Facebook