World's 1st FPGA Portal

PALs were introduced in late 1970 to address speed problem shown by PLA devices. A PAL is opposite to PROM, where AND array is programmable but OR array is fixed. This led PAL faster than PLA devices. PALs usually contain flip-flops connected to the OR-gate outputs to implement sequential circuits. Registered or combinational output functions are modeled in a sum of product form. Each output is a sum (logical or) of a fixed number of products (logical and) of the input signals. PAL architecture has feedback terms. The outputs of the fixed "or" array are fed back to some of the inputs of the "and" array.

Image Courtsey: poppy.snu.ac.kr/~kchoi/class/lc_intro/programmable_logic.pdf

Because of this feedback, it is possible to use the results of the sum of products as inputs in order to create more complex, multi-level logic designs. PAL devices are programmed by blowing the fuses permanently using over voltage.
There are different types of PAL devices available. These are:
• Exclusive-OR PALs
• Asynchronous PALs
• Complex PAL Devices
The advantage of X-OR PALs is parity and arithmetic operations become easy and customized.

Image Courtsey: en.wikipedia.org/wiki/Programmable_Array_Logic

PLD Advantages:
• Reduce IC package count
• Board space
• Power
• Shorten design time
• Allow for future changes (maintainability)
• Improve reliability (fewer packages)
• Faster
• Smaller inventory