GAL - Generic Array Logic

Generic array logic was introduced by lattice semiconductor Co. in 1983. GAL offered CMOS electrically erasable PROM (EPROM, E2PROM) variations on the PAL concept. GAL architecture has reprogrammable AND array, a fixed OR array and reprogrammable output logic. GAL is similar to PAL with output logic macrocells (OLMCs), which provide more flexibility. Output logic macrocell can be configured either for a combinational output of for a registered output. GAL can be erased and reprogrammed and usually replace a whole set of different PALs.

Image Courtesy: poppy.snu.ac.kr/~kchoi/class/lc_intro/programmable_logic.pdf

The reprogrammable array is essentially a grid of conductors forming rows and columns with an electrically erasable CMOS (E2CMOS) cell at each cross-point, rather than a fuse as in a PAL. Each column is connected to the input of an AND gate, and each row is connected to an input variable or its complement. Any combination of input variables or complements can be applied to an AND gate to form any desired product term by programming each E2CMOS cell to be either ‘ON’ or ‘OFF’. Each macrocell contains an edge-triggered D-type flip-flop and a pair of configurable multiplexers. The control fuses for the GAL macrocells allow each macrocell to be configured in one of three basic configurations. These configurations correspond to the various types of I/O configurations found in the PAL devices that the GAL is designed to replace.

Image Courtesy: poppy.snu.ac.kr/~kchoi/class/lc_intro/programmable_logic.pdf