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As the technology surrounding programmable devices improved, new devices were developed which combined several PLDs together on a single integrated circuit to form complex programmable logic devices, CPLDs. CPLD was introduced in late of 1970 with extension of SPLD devices. The concept is to have a few PLD blocks or macrocells on a single device with a general-purpose interconnect in-between. Basically, a CPLD consists of several blocks, each of which is a PLD, which are connected together. I/Os of each of the PLD blocks are connected by a global interconnect array. Each logic block contains 4 to 16 macrocells depending on the vendor and the architecture. A macrocell on most modern CPLDs contains a sum-of-products combinatorial logic function and an optional flip-flop. The combinatorial logic function typically supports four to 16 product terms with wide fan-in. In other words, a macrocell function can have many inputs, but the complexity of the logic function is limited. CPLDs are generally best for control- oriented designs due in part to their fast pin-to-pin performance. The wide fan-in of their macrocells makes them well-suited to complex, high-performance state machines. CPLD has less flexible internal architecture and the delay through a CPLD (measured in nanoseconds) is more predictable and usually shorter. In addition to programming the individual SPLD blocks, the connections between the blocks can be programmed by means of the programmable interconnection matrix, which give greater flexibility to user and become more popular among designers. The devices are programmed using programmable elements that, depending on the technology of the manufacturer, can be EPROM cells, E2PROM cells, or Flash EPROM cells. The Figure below shows general architecture of CPLD devices.