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FPGA Design Best Practices for Teambased Uncomplicated

Distributed Feeds - August 22, 2015 - 5:58am

FPGA Design Best Practices for Teambased Design Uncomplicated

FPGA Design Best Practices for Teambased Design Uncomplicated

“The amount of design wins and early adoptions are ahead of wherewe expected them to be,” says Gavrielov. “We’re definitely ahead of plan in terms of yield,” adds Gavrielov,”we’re not seeing yield issues on HPL. It’s a high k metal gateprocess but it’s a less complex process than the HP process – ithas less mask steps.” He attributes the high yields to the “very intimate” linkage inprocess development with TSMC and to the decision Xilinx made to use TSMC’s HPL processrather than the LP and HP processes chosen by companies which havestruggled. He adds that there are aspects of the HP process wh

As of third week of Feb. 2010, Superpro5000/5004GP device support reached 58,149. This is the largest number in the industry today. So, what does this number mean and how is Xeltek able to support such a large number of devices?

VLSI Field is highly technology intensive and dynamic field with great emphasis on research and development. With each quarter technology node is shrinking, new doping strategies and methodologies are taking shape so does new design and implementation flow are making inroads in day-today VLSI design activities. Academia can only teach basics of VLSI but to be successful in once career a person has to undertake exhaustive and current VLSI flow training.

Fifth, Course cost should not be more than 2-3 month of starting salary which is currently Rs20,000 pm as then recovery time of the course cost become large.

Third, Make sure training will be given industry standard Cadence, Mentor Graphics or Synopsis tools.

In light of above discussion if an engineer take care of following points before deciding on choosing VLSI finishing school their career in VLSI field can be highly rewarding-

The end result is that, using Xilinx s stacked silicon interconnect (SSI) technology, heterogeneous Virtex-7 HT devices deliver theindustry s highest bandwidth FPGAs, featuring up to sixteen 28Gbps and seventy-two 13.1 Gbps transceivers, making them the onlysingle-package solutions for addressing key Nx100G and 400G linecard applications and functions. Combined with Xilinx s leading100G gearbox, Ethernet MAC, OTN and Interlaken IP, Virtex-7 HTdevices provide customers with the levels of system integrationthey need to meet space, power and cost challenges as theytransition to CFP2 optical modul

Categories: Planet FPGA

FPGA Prototyping By Verilog Examples Xilinx Spartan3 Version

Distributed Feeds - August 22, 2015 - 5:55am

FPGA Prototyping By Verilog Examples Xilinx Spartan3 Version

FPGA Prototyping By Verilog Examples Xilinx Spartan3 Version

“The amount of design wins and early adoptions are ahead of wherewe expected them to be,” says Gavrielov. “We’re definitely ahead of plan in terms of yield,” adds Gavrielov,”we’re not seeing yield issues on HPL. It’s a high k metal gateprocess but it’s a less complex process than the HP process – ithas less mask steps.” He attributes the high yields to the “very intimate” linkage inprocess development with TSMC and to the decision xilinx made to use TSMC’s HPL processrather than the LP and HP processes chosen by companies which havestruggled. He adds that there are aspects of the HP process wh

The end result is that, using xilinx s stacked silicon interconnect (SSI) technology, heterogeneous Virtex-7 HT devices deliver theindustry s highest bandwidth FPGAs, featuring up to sixteen 28Gbps and seventy-two 13.1 Gbps transceivers, making them the onlysingle-package solutions for addressing key Nx100G and 400G linecard applications and functions. Combined with Xilinx s leading100G gearbox, Ethernet MAC, OTN and Interlaken IP, Virtex-7 HTdevices provide customers with the levels of system integrationthey need to meet space, power and cost challenges as theytransition to CFP2 optical modul

Rapid prototyping techhniques can help product designers and developers come out with better quality produtcs. Here are just some of the brenefits of rapid prototyping:

2. prototyping can be used to gain a better understanding of the kind of product requiired in the early stagse of developmment. It can help dersigners keep track of the design improvements and possibly test out its effectivity with a control group.

It takes teamwork to achiweve rapid prototypping and the application of its principls in a particular fild. Basically, most of the tasdks are done during the desiggn schematic prcess. It is now a part of any srensitive productions to do rappid prototyping befre decisding on how the project or proudct will make or break it own future in the market. Or in case of surgical applicaations, it aids in the crucial steps the specialists will take part in a life-threatening solution rapid prototyping can offer.

Categories: Planet FPGA

Advanced FPGA Design Architecture Implementation and Optimization Realistic

Distributed Feeds - August 22, 2015 - 3:50am

Advanced FPGA Design Architecture, Implementation, and Optimization Realistic

Advanced FPGA Design Architecture, Implementation, and Optimization Realistic

If performed correctly, the outcomes of your Search engine optimization efforts are especially impressive. Those that practice what some refer to as “ethical” and “correct” Search engine optimization are known as White Hat SEO’s. One of the most critical for Search engine optimization would be to follow the rules and you will not have anything to worry about.

Watch out for Search engine optimization Tools and software program that’s outdated and completely useless. At all times study just before you acquire any Search engine optimization software program mainly because the search engine Algorithms are continuously changing thereby enhancing their search technologies to offer one of the most relevant outcomes for their users. Search engine optimization tools for Google, MSN and Yahoo are various. Search engine optimization tools for press release optimization had been also launched by PRWeb at the end of June known as Search engine optimization Wiza

Most hardcover books on the subject of Search engine optimization are preferred viewed as a vehicle to assist the beginner comprehend the procedure of search engine optimization. This is simply because the principles behind Search engine optimization aren’t simple and easy. They’re highly informative and most webmasters are involved in Search engine optimization and employing it. White hat and black hat Search engine optimization are two opposing views of how you can do search engine optimization. In a nutshell, Search engine optimization are strategies that aim to increase the position or ran

Too regularly, visual style and Search engine optimization are perceived as a mutual sacrifice. Pay-per-click and Search engine optimization are targeted to obtain your webpage placed as close to the top of search engine outcomes as doable. Pay-per-click price cash, but the clicks from Search engine optimization price you absolutely nothing. Search engine optimization are regarded as as the primary aspects in enhancing the visitors of one’s web page. Both, PPC and Search engine optimization are very important. The truth is, essentially the most rewarding component of Search engine optimization

Categories: Planet FPGA

Learning Verilog for FPGAs: Flip Flops

Distributed Feeds - August 20, 2015 - 9:00am

Last time I talked about how to create an adder in Verilog with an eye to putting it into a Lattice iCEstick board. The adder is a combinatorial circuit and didn’t use a clock. This time, we’ll finish the demo design and add two clocked elements: a latch that remembers if the adder has ever generated a carry and also some counters to divide the 12 MHz clock down to a half-second pulse to blink some of the onboard LEDs.

Why Clocks?

Clocks are an important part of practical digital design. Suppose you have a two input AND gate. Then imagine both inputs go from zero to one, which should take the output from zero to one, also. On paper, that seems reasonable, but in real life, the two signals might not arrive at the same time. So there’s some small period of time where the output is “wrong.” For a single gate, this probably isn’t a big deal since the delay is probably minuscule. But the errors will add up and in a more complex circuit it would be easy to get glitches while the inputs to combinatorial gates change with different delays.

The most common solution to this is to only “look” at the signals (and store them in a flip flop) on a clock edge (usually, just the rising edge). Now the circuit will work fine if the longest delay from one flip flop’s output to the next flip flop’s input is less than the period of the clock. This makes things much simpler to design.

If you need a refresher on flip flops, they are elements that remember a single bit. A D flip flop will remember its input (named D) at the clock edge and hold that output until the next clock edge. There are other kinds of flip flops, like the T flip flop (which toggles state) or the JK flip flop which can perform several functions. With Verilog, you generally won’t create flip flops directly, but will let the compiler infer them from your code.

Let’s jump right in with some examples. I’ll explain these each in more details as we go. Consider this code:

reg myoutput; wire myinput; always @(posedge clk) myoutput<=myinput;

This would infer a D type flip flop. The compiler will recognize other types, too. For instance:

reg myoutput; wire myinput; always @(posedge clk) myoutput<=myinput?~myoutput:myoutput;

This would infer a T flip flop. Usually, though, the inference is not this direct. The input might be a logic expression. The compiler can also infer counters which are lots of flip flops:

reg [3:0] ctr; always @(posedge clk) begin if (ctr_reset) ctr<=4'b0; else ctr<=ctr+1; end

Just as using the plus operator allowed the Verilog compiler to do the best thing for an adder, the expression above will let it build an efficient counter without you having to worry about the details. You can build a counter out of individual modules that infer flip flops (or modules that your tool provides for you) but it is better to leave the details to the compiler.

Building a Flip Flop

The demo circuit had three distinct parts: the binary adder circuit from last time is already done. Another part of the example design is to provide an output that latches when a carry is generated. Here’s the part of the code that does that:

reg carrylatch; // latch carry result always @(posedge clk) begin if (reset==1'b1) carrylatch<=1'b0; else begin if (carry) carrylatch<=1'b1; end end

In English, this says that when the clock has a rising edge, check to see if the reset line is high. If it is, clear the carry latch. Otherwise, check to see if the carry is set and if so, set the carry latch. It will remain set until a reset clears it.

The Verilog tool will recognize this is a flip flop with synchronous reset. If you get really concerned about performance, you may want to investigate if your FPGA does better with an asynchronous reset and learn how your tool can be told to do that instead. But for now, this is sufficient. The realization will probably be a D type flip flop with a rising edge-sensitive clock input and a clock enable tied to the carry line. The D input will be tied to a logic 1.

Key Verilog Point #2: Blocking vs Non-Blocking Assignments

Did you notice that some assignments use = and some use <=? This is an important Verilog feature. When you are using assignments, you always use the equal sign. If you are writing a sequential block, you almost never want to use the single equal sign, even though Verilog will allow this. Here’s why:

always @(posedge clk) begin a<=1’b1; b<=a; end

Because the nonblocking assignment (<=) appears, the value of b will become whatever a was at the moment the clock edge occured. That is, all the assignments in the block happen all at one time. In simulation, that means they happen at the end statement since simulations have to pretend everything happens in parallel. In an FPGA, parallel execution is just how the hardware works.

The problem is, if you do not use a non-blocking assignment. Suppose we had:

always @(posedge clk) begin a=1’b1; b=a; end

The Verilog compiler is smart enough to know that b should equal 1 in this case and has to generate extra circuitry (a latch) to make sure b isn’t set at the same time as a. This can cause lots of timing issues and unless you are sure you need to do it and understand the ramifications, you should avoid it at all costs.

Key Verilog Point #3: Default Net Types

You may notice that some of the variables in the Verilog code are of type wire and some are of type reg. A wire has to be constantly driven to some value. A reg is more like a regular variable. A reg may, but doesn’t always, infer a flip flop. However, you can set a value in a reg and it sticks.

One problem you wind up with in Verilog is that if you make up a name, the compiler (by default) will assume you mean for it to be a wire unless you tell it otherwise. That sounds handy, but the problem is if you misspell a name, it just becomes a new wire and then you can’t figure out why your code doesn’t do what you want.

The answer is to always include this at the front of a Verilog file:

`default_nettype none

This causes the compiler to throw an error if you use an undeclared net. That will save you a lot of debugging time wondering why things aren’t working.

Counting and Dividing

The remainder of the Verilog takes the 12MHz clock and uses it to drive a 16 bit counter. When the counter overflows, another counter increases. When that counter reaches 91, the secondary counter goes to zero. This takes roughly 1/2 second at 12MHz.

You can figure that out by noting that 12MHz is 83 ns or .000083 us. A 16-bit counter will overflow on the 65536th count (two to the 16 power). Do the math and that comes out to nearly 5.5ms per overflow. If you let the secondary counter go to 91, that will take almost 497ms. If you go to 92, you go over (502 ms). Note that counting to 91 (or 92) only takes a 7 bit counter. A graphical representation of the situation is shown here with the code for it below.

// The 12MHz clock is too fast // The first counter will / 2^16 (about 5.46ms) // Then the second counter goes to 91 which is 0.497s // close enough to 1/2 second for our purpose always@(posedge clk) begin if (reset==1'b1) begin cnt1<=0; cnt2<=0; half_sec_pulse<=0; dec_cntr<=0; end else if (runstop==1'b0) // don't do anything unless enabled begin cnt1 <= cnt1 + 1; if (cnt1 == 0) if (cnt2 == 91) begin cnt2 <= 0; half_sec_pulse <= 1; end else cnt2 <= cnt2 + 1; else half_sec_pulse <= 0; if (half_sec_pulse == 1) dec_cntr <= dec_cntr + 1; // count half seconds end end

(Note: as mentioned in the comments below, there’s nothing special about a 16-bit counter. I just wanted to show a nested counter, but since this example doesn’t use the intermediate clock, you could have just as easily made a single longer counter to do the job with one division. The FPGA doesn’t care if you make a 2 bit counter or a 60 bit counter unless you run out of resources.)

This is a form of sequential circuit and the counters will turn into a chain of flip flops when synthesized. Here’s the definition for the counters:

// Manage 12MHz clock reg [15:0] cnt1; reg [6:0] cnt2; reg [1:0] dec_cntr; reg half_sec_pulse;

The counter declarations look like arrays, but they aren’t (Verilog does support arrays, but these are not arrays). The numbers in square brackets are telling you the number of bits in the value. So cnt1 has 16 bits numbered from 15 (the most significant) to 0 (the least significant).

We’ll use the array-like bit notation and the assign statement to make some LEDs blink too:

// Make the lights blink assign LED4 = (dec_cntr == 2); assign LED5 = dec_cntr[0]; Updating the Test Bench

Since the new design requires a clock, the testbench has to provide it. It would be very annoying to have to write each clock transition. Luckily, you don’t have to. Here’s how the clock generation works:

always begin #1   clk<=~clk; end

In English, this says: At all times, you should delay one clock cycle (the #1) and then invert the clock signal and keep doing that forever. Another item to consider is the FPGA reset:

rs=1'b0; // run/stop reset=1'b1; #10 reset=1'b0;

This bit of code sets the reset line, holds it for 10 clock cycles, and then clears it.

At the end of the test bench is a 400 cycle delay just to let the counters do something.

Simulation Specifics

There’s one small problem with the simulation. The 12 MHz divider won’t do anything interesting in “only” 400 cycles. It isn’t uncommon to change magic numbers to smaller values when simulating. In this case, I change the primary counter increment to 8000 hex so it will flip every other clock cycle and then changed the test for 91 down to a more reasonable value.

verilog1There are several ways you can do this, but to stay simple, I just commented out the real versions and later I’ll remove the comments and comment out the simulation versions.

You can see the entire code on EDAPlayground and you can even run the simulation from there. The waveform shown here will appear. If you want to know more about how it all works, check out the video and I’ll walk through it step by step.

Next Time

Next time, I’ll show you how to take the Verilog (which should work since it simulates correctly) and push it down to the FPGA board. If you’ve been paying attention, you should have at least one serious question: How do I tell someone that LED1, for example, maps to the LED on the board? That’s a great question, and I’ll answer it next time. Here’s a clue though: It doesn’t depend on the name of the net. I could have called that signal BigJim and I’d still be able to map it to the LED. If you plan to work along, you can get a head start by installing the open source tool kit now. Of course, if you don’t have an iCEstick, that won’t do you much good unless you just want to dry run the tools.

Selected Tutorials

If you are looking for a detailed Verilog tutorial, try these:

  • Doulos (host of EDAPlayground) has a very professionally done set of tutorials
  • Another tutorial set up as a self study course
  • The creator of EDAPlayground has a series on YouTube that would be helpful, especially if you are using EDAPlayground

You can also read the next post in this series.

Categories: Planet FPGA


Distributed Feeds - August 20, 2015 - 12:17am



JTAG is a method for testing connections on printed circuit boards (PCBs) that are implemented at the integrated circuit (IC) level. It is very difficult to test complex circuits with traditional in-circuit testers. Because of physical space constraints and inability to access very small components and BGA devices, the cost for board testing has increased significantly. jtag is an elegant solution to overcome problems with physical in-circuit testers.

“The amount of design wins and early adoptions are ahead of wherewe expected them to be,” says Gavrielov. “We’re definitely ahead of plan in terms of yield,” adds Gavrielov,”we’re not seeing yield issues on HPL. It’s a high k metal gateprocess but it’s a less complex process than the HP process – ithas less mask steps.” He attributes the high yields to the “very intimate” linkage inprocess development with TSMC and to the decision xilinx made to use TSMC’s HPL processrather than the LP and HP processes chosen by companies which havestruggled. He adds that there are aspects of the HP process wh

The end result is that, using xilinx s stacked silicon interconnect (SSI) technology, heterogeneous Virtex-7 HT devices deliver theindustry s highest bandwidth FPGAs, featuring up to sixteen 28Gbps and seventy-two 13.1 Gbps transceivers, making them the onlysingle-package solutions for addressing key Nx100G and 400G linecard applications and functions. Combined with xilinx s leading100G gearbox, Ethernet MAC, OTN and Interlaken IP, Virtex-7 HTdevices provide customers with the levels of system integrationthey need to meet space, power and cost challenges as theytransition to CFP2 optical modul

Categories: Planet FPGA

Learning Verilog for FPGAs: The Tools and Building an Adder

Distributed Feeds - August 19, 2015 - 9:01am

Over the last year we’ve had several posts about the Lattice Semiconductor iCEstick which is shown below. The board looks like an overgrown USB stick with no case, but it is really an FPGA development board. The specs are modest and there is a limited amount of I/O, but the price (about $22, depending on where you shop) is right. I’ve wanted to do a Verilog walk through video series for awhile, and decided this would be the right target platform. You can experiment with a real FPGA without breaking the bank.

In reality, you can learn a lot about FPGAs without ever using real hardware. As you’ll see, a lot of FPGA development occurs with simulated FPGAs that run on your PC. But if you are like me, blinking a virtual LED just isn’t as exciting as making a real one glow. However, for the first two examples I cover you don’t need any hardware beyond your computer. If you want to get ready, you can order an iCEstick and maybe it’ll arrive before Part III of this series if published.

I’m not going to directly try to teach Verilog. If you know C you can pick it up quickly and if you don’t there are plenty of text-based and video-based tutorials to choose from (I’ll add a few at the end of this post). However, I will point out a few key areas that trip up new FPGA designers and by following the example code, you’ll be up to speed in no time.

Choose a Verilog Simulator EDA Playground Screenshot

EDA Playground Simulates Verilog in the Browser

For part I, you need a Verilog simulator. I’m going to use EDAPlayground because it is free and it will run in your browser. No software to set up and no worry if you use some crazy operating system (like Windows). If you have a modern browser, you are all set.

I know some people don’t want to work on the Web or don’t want to create an account (honestly, though, this will just be tutorial code and making up a disposable e-mail address is easy enough). If you just can’t bear it, you can run all the examples on your desktop with Icarus Verilog (using GTKWave to display the results). I just won’t be talking about how to do that. You can read the Icarus introduction if you want to go that route. I still suggest you stick with EDAPlayground for the tutorial.

For the FPGA tools used in Part III, I’m using the open source Icestorm tools. I tried using the Lattice tools and it was heartbreakingly difficult to get them installed and licensed. I’ll have more to say about that in part III.

About the Target Hardware

The IceStick has a modest FPGA onboard. From its manual, it has the following features:

  • High-performance, low-power iCE40HX1K FPGA
  • FTDI 2232H USB device allows iCE device programming and UART interface to a PC
  • Vishay TFDU4101 IrDA transceiver
  • Five user LEDs (one green and four red)
  • 2 x 6 position Diligent Pmod compatible connector enables many other peripheral connections
  • Discera 12Mhz MEMS oscillator
  • Micron 32Mbit N25Q32 SPI flash
  • 16 LVCMOS/LVTTL (3.3V) digital I/O connections on 0.1” through-hole connections

The FPGA isn’t huge, but it is big enough to host a simple CPU (we covered the CPU earlier). We aren’t going to start with a CPU, though. We’ll start with something much more simple.

Let’s Build an Adder

There are two main kinds of circuits you build on any FPGA: combinatorial and sequential. The difference is simple: combinatorial logic is all logic gates. The past state of the circuit doesn’t matter. Given a certain set of inputs, the outputs will be the same. A sequential circuit (which almost always has a flip flop in it) has some memory of a previous state that changes the output. I wanted to show examples of both and how you map them to the board.

addThe example circuit we’ll build has three major parts. The first is a two-bit adder circuit that shows a binary sum and carry on two of the board’s five LEDs. This is a simple combinatorial circuit. It doesn’t make use of the onboard 12MHz clock. The other two portions will. The first sequential circuit will be a simple memory that latches true if a carry has ever been generated by the adder (after a reset, of course). The other sequential circuit is a set of counters that combine to provide a 1/2 second pulse from the 12MHz clock.

Verilog Versus Schematic Entry

For simple circuits, it is tempting to just draw a schematic like the one above and either machine translate that to the FPGA or hand translate it to Verilog. Some tools support this and you may think that’s the way to go. I know I did when I got started.

The truth is, through, that after you move away from simple things, the schematics can be very painful. For example, think of a seven segment decoder. If you took a few minutes you could probably work out the AND OR and NOT gates required to perform the function (that is, convert a four-bit binary number to a seven segment display). But it would take a few minutes.

If you use Verilog, you can take a simple approach and just write out the gates you want. That will work, but it is usually not the right answer. Instead, you should describe the circuit behavior you want and the Verilog compiler will infer what circuits it takes to create what you need. For the seven segment decoder this could be as simple as:

always @(*) case (number) 4'h0: dispoutput <= 7'b1111110; 4'h1: dispoutput <= 7'b0110000; 4'h2: dispoutput <= 7'b1101101; . . .

I promised I’d point out some of the stranger points of Verilog, so let’s look at that in a little more detail. The always statement tells Verilog that the code following should execute whenever any of the inputs you use in it change. This infers a combinatorial circuit since there is no clock. The case statement is like a switch statement in C. The funny looking numbers are four bit hex (4’h1) and 7 bit binary (7’b1101101). So the code instructs the FPGA (or, more accurately, the Verilog compiler) to examine the number and set dispoutput based on the input.

The <= character, by the way, are a non-blocking assignment. You could also use an equal sign here to create a blocking assignment. For now, the difference doesn’t matter, but we’ll revisit that topic when working with a sequential design.

From this description of what you want, the Verilog compiler will infer the right gates and may even be able to perform some optimizations. A key difference between an FPGA and building things on a microcontroller has to do with parallelism. If you wrote similar C code on, say, an Arduino, every copy of it would take some execution time. If you had, for example, 50 decoders, the CPU would have to service each one in turn. On the FPGA you’d just get 50 copies of the same circuit, all operating at once.

Key Verilog Point #1: Verilog isn’t Executable (Except when it is)

That’s a really important point. With an FPGA, the circuitry that drives each display just works all the time. Sure, there is a small delay through the gates (probably picoseconds) but that’s true even with discrete circuitry. It isn’t because the FPGA is executing lines of Verilog code or some equivalent structure. The Verilog becomes connecting wires that wire up circuit elements just as though you had a sea of gates on a PCB and you connected them with wire wrap.

There is an exception to this. During simulation, Verilog does act like a programming language, but it has very specific rules for keeping the timing the same as it will be on the FPGA. However, it also allows you to write constructs that would not be transferable to the FPGA. For example, a subroutine call doesn’t make sense in hardware, but you can do it during simulation. In general, you want to avoid non-synthesizable Verilog except when writing your testbench (the driver for your simulation; I’ll talk more about it in a minute).

Look back at the adder schematic. The sum is a simple XOR gate and the carry is an AND gate. I can express that in Verilog, if I want to, like this:

assign carry=inA&inB; assign sum=inA^inB;

It is smarter, though, to let Verilog figure that out. I can make a variable with two bits in it like this:

reg [1:0] fullsum;

Then I could say:

assign fullsum={1’b0, inA} + {1’b0, inB}; assign carry=fullsum[1]; assign sum=fullsum[0];

The braces turn the one bit wires inA and inB into two bit quantities. In this simple example, I might have actually stuck to the first method, but if you think back on the 7 segment decoder, you’ll see it makes sense to use this inferring style where possible.

Modules and Definitions

When you watch the video below or browse the code, you’ll notice there’s a few minor things I glossed over. For one, all of this code lives in a module. You can think of a module loosely as a subroutine or, better, a C++ class. Other modules can create copies of a module and map different signals to its inputs and outputs. There’s also definitions of all the nets used (we already talked about wires and regs):

module demo( output LED1, output LED2, output LED3, output LED4, output LED5, input PMOD1, // input A input PMOD2, // input B input PMOD3, // run/stop input PMOD4 // reset ); // Alias inputs wire inA; wire inB; assign inA=PMOD1; assign inB=PMOD2;

Note that I wanted the signals to have names associated with the physical hardware (like LED1 and PMOD2) but then later I wanted to use more meaningful names like inB. The assign statement makes this connection. This is a simple use of that statement. If you recall, one way to build the adder was to assign two bits using an expression. That kind of usage is far more common.

A Test Bench Makes The Simulation Possible

Before you commit your design to an FPGA, you’ll probably want to simulate it. Debugging is much easier during simulation because you can examine everything. When the Verilog simulator runs, it follows rules about timing that take into account how everything runs at the same time, so the behavior should be exactly what your FPGA will do.

The only thing many simulators won’t do is account for things like timing on the chip itself (although with the right tools, you can simulate that too). For example, your design may depend on an input changing before a clock edge (the set up time on the flip flop, for example) but because of the routing on the chip, the input won’t change in time.

This kind of timing violation is a real problem with large chips and high speeds. For this sort of small circuit, it shouldn’t be an issue. For now, we can assume if the simulation works, the FPGA should behave in the same way.

To test our code, we need a testbench which is just a way to say a piece of Verilog code that works like the outside world to our unit under test (in this case, the whole design). The code will never synthesize, so we can use strange Verilog features that we don’t normally use in our regular code.

The first thing to do is create a module for the testbench (the name isn’t important) and create an instance of the module we want to test:

`default_nettype none module tb; reg a, b; wire led1, led2, led3, led4, led5; demo dut(led1,led2,led3,led4,led5,a,b);

Note that there is a reg for each input we want to feed the device under test and a wire for each output it will drive. That means all of those reg variables need to be set up to our test conditions.

The variables need to be initialized. Verilog provides an initial block that is usually not valid for synthesis, but will be the main part of most test benches. Here’s the first part of it:

initial begin $dumpfile("dump.vcd"); $dumpvars(0, dut); a=1'b0; b=1'b0;

The two $ statements tell the testbench to dump variables from the device under test to a file called dump.vcd (this is where EDAPlayground looks for it, too, so don’t change it unless you are using your own Verilog simulator). We’ll be able to examine anything that gets dumped. You can also print things using $display, but I didn’t do that in this test.

The next thing you need is some test case stimulus. In the case of the counters, you don’t need anything other than the clock. But the adder-related circuitry needs some values:

#2 a=1'b1; #4 b=1'b1; #4 a=1'b0; #4 b=1'b0; #4 $finish; end

So at first, a=1 and b=0. Then after 4 cycles, a=1 and b=1. After another 4 cycles a=0, b=1. Then a=0, b=0. The $finish statement causes the simulation to end. Without this, the clock generator will cause the simulation to keep going forever.

You can find the code and the testbench on EDAPlayground (you can even run the simulation from there). When you run the simulation, a waveform will appear (see below). If you want to know more about how it works, check out the video below and I’ll walk through it step by step.


Next Time

In tomorrow’s installment of this series, I’ll show you how to add sequential (clocked) logic to the design and the testbench. Using clocks are an important part of making practical digital designs, as you’ll soon see. I’ll also have a few more Verilog key points.

Selected Tutorials

If you are looking for a detailed Verilog tutorial, try these:

  • Doulos (host of EDAPlayground) has a very professionally done set of tutorials
  • Another tutorial set up as a self study course
  • The creator of EDAPlayground has a series on YouTube that would be helpful, especially if you are using EDAPlayground

You can also read the next post in this series.

Categories: Planet FPGA

Graphics on Cyclone V SoCKIT FPGA

Distributed Feeds - August 16, 2015 - 5:43pm

While exploring project ideas for DECA, a new Altera MAX10 FPGA board from Arrow/Terasic (I will cover it in a later series), I’m curious about FPGA graphics capability. I checked it out with a Cyclone V SoCKIT I had since last year.

I found Terasic SoCKIT VIP (Altera Video and Image Processing Suite) reference design from RocketBoards. It does a really good job to demonstrate video features of VIP. I modified the FPGA design to address more on graphics, by removing Logo generator I don’t need, and adding a frame reader of 800×480 pixels and 32 bit per pixel to support graphics, and reusing the first frame reader of 640×480 pixels for graphics too.

The following picture shows the FPGA hardware setup, basically VIP, and software process for graphics rendering.
FPGA Hardware Setup and Software Process

The rendering process consists of two threads handing graphics; and each thread corresponds a VIP Frame Reader, as indicated on the right side of FPGA setup of above picture.

  • The first 640×480 pixel graphics loops through a sequence of PNG files to show a snowfall. Except for transferring decoded PNG data directly into the frame buffer, it doesn’t do much else. The main parent process also adjusts this graphics’ position such that it bounces around within the screen.
  • The second 800×480 pixel graphics renders a Automotive HMI design. The graphics is using XFree86 frame buffer pipeline and proprietary engine.

The following video click shows the process showing the graphics: turn on the SoCKIT board; bring up ethernet so software application can be downloaded to FPAG and debugged via ARM DS-5 Altera Edition; configure the FPGA; and finally run the graphics application.

This exercise lays a solid foundation for my next tackling to get graphics working on Altera MAX 10 DECA board.

Categories: Planet FPGA

Verilog by Example A Concise Introduction for FPGA Design

Distributed Feeds - August 12, 2015 - 11:27pm

 Verilog by Example A Concise Introduction for FPGA Design

Verilog by Example A Concise Introduction for FPGA Design

“The amount of design wins and early adoptions are ahead of wherewe expected them to be,” says Gavrielov. “We’re definitely ahead of plan in terms of yield,” adds Gavrielov,”we’re not seeing yield issues on HPL. It’s a high k metal gateprocess but it’s a less complex process than the HP process – ithas less mask steps.” He attributes the high yields to the “very intimate” linkage inprocess development with TSMC and to the decision Xilinx made to use TSMC’s HPL processrather than the LP and HP processes chosen by companies which havestruggled. He adds that there are aspects of the HP process wh

As of third week of Feb. 2010, Superpro5000/5004GP device support reached 58,149. This is the largest number in the industry today. So, what does this number mean and how is Xeltek able to support such a large number of devices?

Xeltek SuperPro 5000/5004GP currently supports 58K+ devices and 60K device support maybe already passed while you are reading this article. This is a true milestone and a new standard of the industry unmatched by any other company.

Stand-alone and PC mode programming technology was perfected and made practical by Xeltek and has been in use for the last 6 years. As a result, Xeltek programmers are well adapted for both Engineering development and volume manufacturing. Currently, Xeltek programmers occupy more than 70% of the very large Chinese Engineering and Manufacturing market. Expensive automated programmers have been largely driven out from the Chinese market and replaced by Xeltek SuperPro Stand-alone programmers. Those 2 big brand names have limited presence in the China today because of the dominance of Xeltek pro

Firstly, Find out what kind of flow the institute is teaching as fpga based flow is sheer waste of time and Money as FPGA is just very small part of VLSI Flow.

Categories: Planet FPGA

Simulation steps for Quartus II to burn VHDL code in FPGA

Distributed Feeds - August 3, 2015 - 8:00pm
  1. Open Quartus II software.
  2. click on “New Project Wizard” from file tab
  3. select folder name & project name in the dialog box.
  4. Add file(HDL) if already exist in above selected folder else move to next.
  5. Select the Device family e.g “Cyclone IV GX” and select the available device “EP4CGX15BF14A7”. Click next.
  6. In EDA Tool setting, select “ModelSim- Altera”, format “VHDL”( in this case). click next
  7. Click on new file and select “VHDL File”.
  8. write your VHDL code and save file in same name as your project name.
  9. Click on start analysis and synthesis for errors if any.analysis button
  10. For pin assignment, click on pin planner
  11. In the “location” column type pin_XX, the options for pin no. will be suggested. then click on processing –> start I/o assignment analysis or click on Run I/o assignment analysis as shown assignment
  1. then click on start compilation.simulation bar
  2. successful compilation will generate a .sof file which is to be burned in your FPGA.
  3. Connect your FPGA to PC via USB Blaster (install USB blaster drivers initially).
  4. Go to Tools tab, then click on the programmer icon.
  5. Click on Hardware setup–> select USB Blaster or select Auto Detect.
  6. Click on Add files, to add the .sof file.
  7. Click on start and wait till 100% progress.
Categories: Planet FPGA

Installing Altera USB blaster driver on Windows 8.1 (Installing unsigned drivers)

Distributed Feeds - July 30, 2015 - 4:31am

I started playing around with FPGA development using the Terasic DE0 development board recently and the first problem I encountered was the installation of the USB blaster driver. As far as I know there is no problem in installing the driver on Windows 7 but if you are using Windows 8 or 8.1 then you probably ran into the problem of Windows not allowing you to install unsigned drivers. I lost a significant amount of time to make the driver work on Windows 8.1 so to speed things up for you, here is what you do.

First, you need to obtain the driver to be installed. You probably already have it if you installed Quartus II, it comes with the installation. On my system it is located in:


Now, if you follow the instruction from Altera USB blaster install you probably get to step 8 of the instructions after which you are not prompted with a window mentioned on step 9. This is due to the fact that Windows 8 doesn’t allow you to install unsigned drivers by default so you need to disable this security option.

press Windows key and type in “Change advanced startup options”, and enter the options. You should see the following window (click on the picture to enlarge)

Advanced startup options - Recovery

Advanced startup options – Recovery – Advanced startup

Go to Recovery and under Advanced startup locate Restart now. Before you click on it save whatever stuff you need to save since the restart is (almost) immediate. After you click on the button you will be prompted with a window providing you with a few options. Choose:

Troubleshoot -> Advanced options -> Startup Settings -> Restart

After restarting you will be prompted with another window that will provide you some other options. Choose:

7) Disable driver signature enforcement 

Having all that in mind, now press the Restart now button from the screenshot above.

After restart try to install the USB blaster driver. Plug in the device, fire up Device Manager, locate the USB-blaster device and click on Update Driver Software.

Update USB blaster software

Update USB blaster software

On the new window that opens choose Browse my computer for driver software.

Manually install driver

Choose to manually install the driver

In the next window, locate the driver and click Next.

Enter/browse for the location of the USB blaster driver. It's in the Quartus II installation folder.

Enter/browse for the location of the USB blaster driver. It’s in the Quartus II installation folder.

After the Window successfully finds the driver you should be prompted with the window:


Click on Install. When the driver installs you should see it installed in the Device Manager:


To check that Quartus II can now use the driver, open up Quartus II and go to:

Tools -> Programmer

A window will open. Click on Hardware Setup:

Quartus II - Programmer window

Quartus II – Programmer window

A new window will open. In the drop down menu choose USB blaster.

Quatus II - Programmer - Hardware setup window

Quatus II – Programmer – Hardware setup window

Click Close. In the Programmer window you should now see the USB blaster selected as a programmer.

Quartus II - Programmer window with USB blaster selected

Quartus II – Programmer window with USB blaster selected

That’s it! The driver is installed and you can now program the FPGA board.

Categories: Planet FPGA

Open Source FPGA Toolchain Builds CPU

Distributed Feeds - July 28, 2015 - 7:31am

When you develop software, you need some kind of toolchain. For example, to develop for an ARM processor, you need a suitable C compiler, a linker, a library, and a programmer. FPGAs use a similar set of tools. However, instead of converting source code to machine language, these tools map the intent of your source code into configuration of FPGA elements and the connections between them.

There’s some variation, but the basic flow in an FPGA build is to use a synthesizer to convert Verilog or VHDL to a physical design. Then a mapper maps that design to the physical elements available on a particular FPGA. Finally, a place and route step determines how to put those elements in a way that they can be interconnected. The final step is to generate a bitstream the chip understands and somehow loading it to the chip (usually via JTAG or by programming a chip or an external EEPROM).

One problem with making your own tools is that the manufacturers typically hold the bitstream format and other essential details close to their chest. Of course, anything can be reverse engineered (with difficulty) and [James Bowman] was able to build a minimal CPU using  an open source Lattice toolchain. The project relies on several open source projects, including  IceStorm, which provides configuration tools for Lattice iCE40 FPGAs (there is a very inexpensive development platform available for this device).

We’ve covered IceStorm before. The IceStorm project provides three tools: one to produce the chip’s binary format from an ASCII representation (and the reverse conversion), a programmer for the iCEstick and HX8K development boards, and database that tells other open source tools about the device.

Those tools blend with other open source tools to form a complete toolchain–a great example of open source collaboration. Yosys does the synthesis (one of the tools available on the EDAPlayground site). The place and route is done by Arachne. The combined tools are now sufficient to build the J1A CPU and can even run a simple version of Forth. If you’ve ever wanted to play with an FPGA-based CPU design, you now have a $22 hardware option and free tools.

Categories: Planet FPGA

Altera’s Stratix 10 is a marvel of high-performance FPGA design

Distributed Feeds - July 27, 2015 - 10:45pm

Together with Xilinx, Altera has been the other half of the two-party system driving the FPGA arms race forward for many years. Big headlines were made when it was recently announced that Intel would would buy Altera in a $6.7 billion cash deal. Among other things, Intel will be acquiring Altera’s new Stratix 10 chip, a device some are calling “the most significant step forward in high-end FPGAs.”

The chip features the revolutionary HyperFlex core fabric architecture built on the Intel 14 nm Tri-Gate process. This equates to a 2X core performance gain over other high-performance FPGAs at up to 70% lower power. The Hyperflex design addresses some of the issues that come in to play at high GHz frequencies. The primary concern is minimizing the so-called propagation delay — the time it takes a signal to travel from one register to the next. There are two components to propagation delay, the logic or gate delay, and the routing or wiring delay.

Normally, one might try to speed things up by widening the buses to move more things in parallel. The downside is that a much larger die is generally needed, and it also consumes more power. Instead, Altera focussed on the routing delay by simply adding more registers. The key is that their ‘hyper-registers’ can be associated not only with each routing segment on the chip, but also with the other amenities like DSP and embedded memory. Unlike general registers, hyper-registers also include the option to be bypassed.

On the design end — not the chip design itself, but rather the design that the user burns into the chip — this bypassing feature allows optimal register location to be automatically programmed in after the ‘place-and-route’ step. The place-and-route is typically what the designer does after creating the circuit (the set of logic elements together with the netlist connecting them), by popping the logic and connections into their desired places and pins on the chip.

Some other features that caught our eye include the integrated quad-core 64 bit 1.5 GHz ARM Cortex-A53 hard processor system, and 10 TFLOPS of IEEE 754 compliant single precision floating point DSP. The heterogeneous 3D System-in-Package (SiP) integration also sounds cool, although I am not really sure what all that entails. It must be good, because with up to 5.5 million logic elements the chip claims itself to be the highest density highest density FPGA fabric available.

Clearly not business analysts, we have nonetheless noted that only a few companies have so far availed themselves of Intel’s 14nm process, with Altera being one of the majors. Apparently, Intel has indicated they will be integrating FPGAs into future Xeon products to add some processor customization capability. Gaining access to Altera’s technology at a deeper level should definitely complement the FPGA packaging services that Intel already provides for customers.

40.712784 -74.005941
Categories: Planet FPGA

Running LEON3 on ZedBoard Tutorial

Distributed Feeds - July 25, 2015 - 3:36am

LEON3? FPGA? ?? ??? soft-core processor ? ? ???, SPARC V8 ????? ???? ??[1]. ?? ??? Cobham Gaisler?? ???? ???, ??/?? ???? ??? ??? ? ?? (GNU GPL ????). RTL? ?? ???? ????? ? ? ????? LEON3? ????. LEON3? ??? ZedBoard? ????, ? ?? ???? ?????. ? ???? ZedBoard? LEON3? ???, ???? ???? ?? ???? ??? ????? ??.

??? XUPV5-LX110T(ML509) ??? OpenSPARC? ???? ??? ????. OpenSPARC? Sun?? ??? ???? ??????[6,7]. OpenSPARC? XUPV5-LX110T? ??? ?? ?? ???? ???[8]. ?? ?? ??? ?? ?????. 10?? ?? ??? ????? ??????, ??? ???? ?? ??? ????? ???. ?? ??? ?? ???? ?? ???, ?? ???? ??? ?? ??? ???. ?? ?? ?? ?? ??? ?? ????? ??. ???? ?? ??? ???????, ISE 10.1 ?? ??? ???? ??? ??? ???. ? ?? ????? ???? ??? ???? ???. ??? Xilinx?? ???? ? ? ???, ???? ?? ?? ??? ???? (VCS, Vera, Debussy). ?? ?? ?? ??? ??? ?? ?? ????.

?? ?? LEON3? ????? ? ???? ???, ???? ??? ?? (??? ???). ?? ??? ??? ???? ?? ??? ? ???. ?????? Realtime Embedded?? ???? ????? ??? ???[10]. LEON3, OpenRISC 1200, Nios2, MicroBlaze ?? ????? ??. LEON3? ?? ??? ???, ???? ?? ?? ????. Realtime Embedded? ?? ??? ? ???? ???, ??? ?? ???? ?? (?? ??), ?? ??? ???? ?, ?? ??? ???? ??? ZedBoard? ?? ????? ??? ?? ???.

1. ZedBoard ??
2. ?? ?? ??
– 1) grlib ???? ? ??
– 2) Xilinx Vivado 2013.4 ??
– 3) ??? ?? ?? ? Digilent ???? ??
3. LEON3 ?? ? ZedBoard? ???
– 1) grlib ?? ?? ??
– 2) LEON3 ??
– 3) ZedBoard? leon3mp.bit ???
4. grmon? ??? LEON3 ?? ? ??? ??
– 1) grmon ??
– 2) grmon? ??? LEON3? ??
– 3) ??? ??? ???? ? ??
5. ??? ??? ?? ? ??
– 1) ?? ? ???? ? ??
– 2) buildroot
– 3) leon linux ??
– 4) mklinuximg
– 5) grmon? ??? LEON3 ??, ??? ??

1. ZedBoard ??
ZedBoard? Zynq-7000 all-programmable SoC? ?? ?? ????[4, 11]. Zynq-7000? all-programmable SoC? ? ??? ????, ZedBoard? ??? ??? ? ??? ?? ??? ????. Zynq-7000? ??? ?? ??? ZedBoard ??? ZC702, ZC706 ?? ??[15]. ?? ???? ZedBoard? ??? ?? ??? LEON3? ?????. ZedBoard? ?? ?? ??? ???? ??? ??? ?? ??[16]. ???? ????? ??? ??????, LEON3? ??? ???? ????? ?? ??? ???? ??. ZedBoard ?? ?? ?? ? ?? ??? The Zynq Book[14], An FPGA Tutorial using the ZedBoard[17], ZedBoard Training and Videos[18], Zynq design from scratch[19]? ???? ??. ? ?? Xilinx Documentation? ? ???? ?? ??? ?? ??. ZedBoard? Zynq-7000? ? ??? LEON3? ??? ?? ?? ???, ? ??? ??? ?? ??? ???? ??.

2. ?? ?? ??
LEON3? ???? ZedBoard? ??? ???? grlib(LEON3 ?? ??), Vivado(?? ??), digilent ????? ???? ???? ??.

1) grlib ???? ? ??
Cobham Gaisler ????? ???, LEON3/GRLIB source code? GRFPU netlist? ??????[20].

$wget $wget $tar -xzvf grlib-gpl-1.4.1-b4156.tar.gz $cd grlib-gpl-1.4.1-b4156 $tar -xzvf ../grlib-netlists-gpl-1.4.1.tar.gz

??? ??? grlib? ???? ??? ??? ??

$cd grlib-gpl-1.4.1-b4156 $tree -L 1 ??? bin ??? boards ??? designs ??? doc ??? lib ??? Makefile ??? netlists ??? software

boards ????? ?? ??? ?? ??? ?? ???, designs ????? ?? ??? ?? ??? ?? ??. designs ?????? make ???? ??? LEON3? ????, ?? LEON3? ?? ? ??. ZedBoard? ??, ./grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702? ????. ?? ?? ? ?? ??? ?? ??? ? ???? ??? README.txt? ???? ???, ?? ???? ??.

2) Xilinx Vivado 2013.4 ??
Xilinx ????? ??? Vivado Design Suite 2013.4 ??? ??????. ??? Vivado Design Suite 2013.4 ??? ???? ??(README.txt ??). ??? ??? LEON3? ?? ? ??? ??? ?? ???.

??? ?? ?? ???, ?? ???? ??? ??? ???? ??? ??? ??.

$tar -xvf Xilinx_Vivado_SDK_2013.4_1210_1.tar $cd Xilinx_Vivado_SDK_2013.4_1210_1 $sudo ./xsetup

? ??? ?? ? ???? ?? ??? ? ??? ??? ???, Xilinx ???? ???? ???[22]. ?????? ?? ??? ?? ???? ??? ?? ??? ?? ???, ? ??? ?? ?? ? ??[16].

???, ??? ?? ???? Xilinx cable driver ?? ??? ???? ???. Ubuntu 14.04.2 Desktop, 64bit?? ? ??? ???? ???? ??? ????. Cable driver? ?? ???? ????.

3) ??? ?? ?? ? Digilent ???? ??
????? USB-UART? ????? ??? ???? ??? ???? ??. CONFIG_USB_SERIAL_CYPRESS_M8=y, CONFIG_USB_ACM=y? ??? ??? ???? ??[23]. ?? ??? ?????, ??? ??? ?? ?? ?? ?????? ?? ???? ??. ?? ?? ??? ??? ??? ? ??? ???? ???? ??[24]. ???? ????? ZedBoard? USB-UART ??? ???? ? /dev/ttyACM0 ??? ??? ? ??.

???? Digilent? ????? ????.

$wget $sudo dpkg -i digilent.adept.runtime_2.16.1-2_amd64.deb

?????? ??? ??????, ??? ?? ?? ? ??. USB-JTAG, USB-UART? ??? ????? ????? ?? 1) ZedBoard? ??? SD ??? ??? ???? ????, ?? ??? ??, 2) ??? ????? ZedBoard? ???? ??? ????? ???? ???.

??? ??? ??? ????(?) ??? ????? ?? ??.

3. LEON3 ?? ? ZedBoard? ???
???? ZedBoard ?? ??? ???? LEON3 ?? ??? ???? ???.
?? LEON3? ???? ZedBoard? ???? ? ??.

1) grlib ?? ?? ??
?? ZedBoard? ???? ????? ./grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702?? ????. ??? ?? ZedBoard? ZC702? ?? ????, ??? ZedBoard? ??? ??? ????? ??[26,27]. ./grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702/leon3mp.xdc ??? ?????? ??.

ZedBoard? ??? ??? ???? ???, ??? grmon? ??? LEON3? ??? ? ??? ?? ??? ????[28].

$./grmon -xilusb -nb -u GRMON2 LEON debug monitor v2.0.65 32-bit eval version Copyright (C) 2015 Cobham Gaisler - All rights reserved. For latest updates, go to Comments or bug-reports to [email protected] This eval version will expire on 10/12/2015 Xilusb: Cable type/rev : 0x3 JTAG chain (2): xc7x020 zynq7000_arm_dap Warning: Failed to call Tcl_Init. Some TCL functions won't be working properly To avoid this warning, see Installation section in the manual about the environment variable GRMON_SHARE AMBA plug&play not found! Failed to initialize target! Exiting GRMON

ZedBoard? ??? ./grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702/leon3mp.xdc? ?? ?????? ??.

?? ?? ?? ??

#set_property PACKAGE_PIN T22 [get_ports {led[0]}] set_property PACKAGE_PIN P17 [get_ports {led[7]}] set_property PACKAGE_PIN P18 [get_ports {led[6]}] set_property PACKAGE_PIN W10 [get_ports {led[5]}] set_property PACKAGE_PIN V7 [get_ports {led[4]}] set_property PACKAGE_PIN W5 [get_ports {led[3]}] set_property PACKAGE_PIN W17 [get_ports {led[2]}] set_property PACKAGE_PIN D15 [get_ports {led[1]}] set_property PACKAGE_PIN E15 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS18 [get_ports {led[6]}] set_property IOSTANDARD LVCMOS18 [get_ports {led[5]}] set_property IOSTANDARD LVCMOS18 [get_ports {led[4]}] set_property IOSTANDARD LVCMOS18 [get_ports {led[3]}] set_property IOSTANDARD LVCMOS18 [get_ports {led[2]}] set_property IOSTANDARD LVCMOS18 [get_ports {led[1]}] set_property IOSTANDARD LVCMOS18 [get_ports {led[0]}] #LEFT btn set_property PACKAGE_PIN G19 [get_ports {button[0]}] #RIGHT btn set_property PACKAGE_PIN F19 [get_ports {button[1]}] set_property PACKAGE_PIN J18 [get_ports {button[2]}] set_property PACKAGE_PIN K18 [get_ports {button[3]}] set_property PACKAGE_PIN N19 [get_ports {switch[0]}] set_property PACKAGE_PIN N20 [get_ports {switch[1]}] set_property PACKAGE_PIN N17 [get_ports {switch[2]}] set_property PACKAGE_PIN N18 [get_ports {switch[3]}] set_property PACKAGE_PIN M15 [get_ports {switch[4]}] set_property PACKAGE_PIN M16 [get_ports {switch[5]}] set_property PACKAGE_PIN P16 [get_ports {switch[6]}] set_property PACKAGE_PIN R16 [get_ports {switch[7]}] #create_clock -name clk100 -period 10.0 [get_ports gclk] set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks clk_fpga_1] set_false_path -from [get_clocks clk_fpga_1] -to [get_clocks clk_fpga_0]

?? ?? ?? ??

set_property IOSTANDARD LVCMOS33 [get_ports led] set_property PACKAGE_PIN T22 [get_ports {led[0]}] set_property PACKAGE_PIN T21 [get_ports {led[1]}] set_property PACKAGE_PIN U22 [get_ports {led[2]}] set_property PACKAGE_PIN U21 [get_ports {led[3]}] set_property PACKAGE_PIN V22 [get_ports {led[4]}] set_property PACKAGE_PIN W22 [get_ports {led[5]}] set_property PACKAGE_PIN U19 [get_ports {led[6]}] set_property PACKAGE_PIN U14 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS18 [get_ports switch] set_property PACKAGE_PIN F22 [get_ports {switch[0]}] set_property PACKAGE_PIN G22 [get_ports {switch[1]}] set_property PACKAGE_PIN H22 [get_ports {switch[2]}] set_property PACKAGE_PIN F21 [get_ports {switch[3]}] set_property PACKAGE_PIN H19 [get_ports {switch[4]}] set_property PACKAGE_PIN H18 [get_ports {switch[5]}] set_property PACKAGE_PIN H17 [get_ports {switch[6]}] set_property PACKAGE_PIN M15 [get_ports {switch[7]}] set_property IOSTANDARD LVCMOS18 [get_ports button] set_property PACKAGE_PIN R16 [get_ports {button[0]}] set_property PACKAGE_PIN N15 [get_ports {button[1]}] set_property PACKAGE_PIN R18 [get_ports {button[2]}] set_property PACKAGE_PIN T18 [get_ports {button[3]}] set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks clk_fpga_1] set_false_path -from [get_clocks clk_fpga_1] -to [get_clocks clk_fpga_0]

2) LEON3 ??
./grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702 ?????? make ???? ??? LEON3? ??? ? ??. LEON3? ??? ???? ./grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702/leon3mp.bit ??? ??? ? ??.

?? Makefile? ???? ??? ?????.
make help ???? ?? ??? ??? ??? ? ??.
?? ??? ????? ?? ?? ?? ???? ??? LEON3? ????.
XUPV5-LX110T(ML509)? ???? make ise?, ZedBoard? ?? make vivado? ????.

$cd ./grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702 $make help interactive targets: make alint-launch : start alint elaboration time linting make avhdl-launch : start active-hdl gui mode make riviera-launch : start riviera make vsim-launch : start modelsim make ncsim-launch : compile design using ncsim make actel-launch : start Actel Designer for current project make ise-launch : start ISE project navigator for XST project make ise-launch-synp : start ISE project navigator for synplify project make quartus-launch : start Quartus for current project make quartus-launch-synp : start Quartus for synplify project make synplify-launch : start synplify make vivado-launch : start Vivado project navigator make planahead-launch : start PlanAhead project navigator make xgrlib : start grlib GUI batch targets: make alint-comp : alint compilation time linting make avhdl : compile design using active-hdl gui mode make vsimsa : compile design using active-hdl batch mode make riviera : compile design using riviera make vsim : compile design using modelsim make ncsim : compile design using ncsim make ghdl : compile design using GHDL make actel : synthesize with synplify, place&route Actel Designer make ise : synthesize and place&route with Xilinx ISE make ise-map : synthesize design using Xilinx XST make ise-prec : synthesize with precision, place&route with Xilinx ISE make ise-synp : synthesize with synplify, place&route with Xilinx ISE make isp-synp : synthesize with synplify, place&route with ISPLever make quartus : synthesize and place&route using Quartus make quartus-map : synthesize design using Quartus make quartus-synp : synthesize with synplify, place&route with Quartus make precision : synthesize design using precision make synplify : synthesize design using synplify make vivado : synthesize and place&route with Xilinx Vivado make planahead : synthesize and place&route with Xilinx PlanAhead make dc : synthesize design usign Synopsys Design Compiler make fm : Formal equivalence check using Synopsys Formality make scripts : generate compile scripts only make clean : remove all temporary files except scripts make distclean : remove all temporary files

make vivado ??? ??? LEON3? ????.

$cd ./grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702 $make vivado

3) ZedBoard? leon3mp.bit ???
?? ?? ?? leon3mp.bit ??? ZedBoard? ??? ??.
make program-zc702 ???? ??? leon3mp.bit? ZedBoard? ???.

$make program-zc702 xmd Xilinx Microprocessor Debugger (XMD) Engine Xilinx EDK 2013.4 Build EDK_2013.4.20131205 Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. XMD% Programming Bitstream -- ./vivado/leon3-zc702/leon3-zc702.runs/impl_1/leon3mp.bit Fpga Programming Progress ............10.........20.........30.........40.........50.........60.........70.........80.........90........Done Successfully downloaded bit file. JTAG chain configuration -------------------------------------------------- Device ID Code IR Length Part Name 1 4ba00477 4 Cortex-A9 2 23727093 6 XC7Z020 JTAG chain configuration -------------------------------------------------- Device ID Code IR Length Part Name 1 4ba00477 4 Cortex-A9 2 23727093 6 XC7Z020 -------------------------------------------------- Enabling extended memory access checks for Zynq. Writes to reserved memory are not permitted and reads return 0. To disable this feature, run "debugconfig -memory_access_check disable". -------------------------------------------------- CortexA9 Processor Configuration ------------------------------------- Version.............................0x00000003 User ID.............................0x00000000 No of PC Breakpoints................6 No of Addr/Data Watchpoints.........4 Connected to "arm" target. id = 64 Starting GDB server for "arm" target (id = 64) at TCP port no 1234 Note:: init_user command is Deprecated. Use ps7_post_config from ps7_init.tcl

?????? ???? ??? ?? ?? ???.


4. grmon? ??? LEON3 ?? ? ??? ??
?? LEON3? ??? ???? ??? ???, ? ? ??? ?? grmon??. grmon? ??? ??? ???, LEON3? ??? LEON3? ??? ????? ??? ???? ??? ??? ? ??. grmon ?? Cobham Gaisler?? ????.

1) grmon ??

$wget $tar -xzvf grmon-eval-2.0.65.tar.gz $export GRMON_SHARE=/path/to/grmon/linux/share

Cobham Gaisler?? ???? grmon? 32bit? ?????? 64bit Ubuntu?? ? ???? ?? ? ??. ?????? ?? ??? ?? ??? ??? ? ???, ?? ??? ???? ??? (??? ??? ???? ??). 32bit? ?????? ??? ??? ?? ???? ??? ? ???. ???? ???? ???? ?? ??? ? ?? ?? ???[29].

2) grmon? ??? LEON3? ??
??? ??? grmon? ??? LEON3? ??? ? ??.

$cd ./grmon-eval-2.0.65/linux/bin $./grmon -xilusb -nb -u

? ?? ??? ??, ???? grmon? Xilinx? USB-JTAG? ???? ???? ???. USB-JTAG? ???? ???? ?? ???. ??? ??? parallel JTAB cable? ???? ??.

3) ??? ??? ???? ? ??
?? ???? ??? ?? LEON3? ??? ????? ???? ??, ?? ???? ?? ??? ???? ?????. ?? ???? ?? ??? ???? ????, grmon? ??? ????.

$wget $./grmon -xilusb -nb -u GRMON2 LEON debug monitor v2.0.65 32-bit eval version Copyright (C) 2015 Cobham Gaisler - All rights reserved. For latest updates, go to Comments or bug-reports to [email protected] This eval version will expire on 10/12/2015 Xilusb: Cable type/rev : 0x3 JTAG chain (2): xc7x020 zynq7000_arm_dap GRLIB build version: 4156 Detected frequency: 83 MHz Component Vendor LEON3 SPARC V8 Processor Cobham Gaisler JTAG Debug Link Cobham Gaisler Generic AHB ROM Cobham Gaisler AHB/APB Bridge Cobham Gaisler LEON3 Debug Support Unit Cobham Gaisler Xilinx MIG DDR2 Controller Cobham Gaisler Generic UART Cobham Gaisler Multi-processor Interrupt Ctrl. Cobham Gaisler Modular Timer Unit Cobham Gaisler General Purpose I/O port Cobham Gaisler AHB Status Register Cobham Gaisler Use command 'info sys' to print a detailed report of attached cores grmon2> load /path/to/image.dsu 40000000 .stage2 10.0kB / 10.0kB [===============>] 100% 40004000 .vmlinux 3.1MB / 3.1MB [===============>] 100% Total size: 3.10MB (1.53Mbit/s) Entry point 0x40000000 Image /tmp/image.dsu loaded grmon2> run Booting Linux Booting Linux... PROMLIB: Sun Boot Prom Version 0 Revision 0 ... Execution Finished, Exiting Please press Enter to activate this console. Sash command shell (version 1.1.1) />ls bin dev etc home init lib mnt proc sbin sys tmp usr var />

??? ?? ??? ?? ??? ? ??.

5. ??? ??? ?? ? ??
???? ??? ???? ?? ??? ??? ?? ????.

1) ?? ? ???? ? ??
??? ???? ???? ???? ? ??? ????. sparc-linux-ct-multilib-0.0.7, leon-buildroot-2013.02-1.0.3, leon-linux-3.10-3.10.58-1.0.4, mklinuximg-2.0.9? ????. sparc-linux-ct-multilib-0.0.7? SPARC? ????? ???? ?????, buildroot? LEON3? ??? ?? ???? ?????. leon-linux? ?? ???? ??? ?? ???? ?????, mklinuximg? ??? LEON3? ?? ? ?? ?? ???? ??? ? ??.

$wget $wget $wget $wget $tar -xvf sparc-linux-ct-multilib-0.0.7.tar.bz2 $tar -xvf leon-buildroot-2013.02-1.0.3.tar.bz2 $tar -xvf leon-linux-3.10-3.10.58-1.0.4.tar.bz2 $tar -xvf mklinuximg-2.0.9.tar.bz2 $export PATH=$PATH:/path/to/sparc-linux-4.4.2-toolchains/multilib/bin

2) buildroot
?? make install ???? ????.

$cd /path/to/leon-buildroot-2013.02-1.0.3 $make install

???? make build ???? ???, buildroot configuration? ????.

$make build

??? ?? buildroot? ????.

Target Architecture: SPARC Target Architecture Variant: v8 Toolchain - Toolchain path (New): /path/to/sparc-linux-4.4.2-toolchains/multilib Filesystem images - cpio the root filesystem: yes

????? Save an Alternate Configuration File? ??? ??? ????. make build ???? ?? ???? ???? ./buildroot-git/output?? ??? ??? ??? ? ??.

$make build $ls ./buildroot-git/output rootfs.cpio rootfs.tar

3) leon linux ??
???? leon linux? ????. leon-linux-3.10-3.10.58-1.0.4.tar.bz2 ???? ??? ??? ????, ?? ????? ??.

$cd /path/to/leon-linux-3.10-3.10.58-1.0.4/ $git clone git://

LEON3?? ???? ??? ? ??? ??? ?? ??? ????.

$cd linux $git checkout v3.10 $patch -p1 < ../patches/0001-sparc32-leon-older-LEON3-4-designs-need-explicit-dat.patch $patch -p1 < ../patches/0002-sparc32-leon-prevent-long-uart-fifo-discovery-loop.patch $patch -p1 < ../patches/0003-Avoid-using-UART-during-PHY-initialization.patch $patch -p1 < ../patches/0004-spi-add-support-for-aeroflex-gaisler-spimctrl.patch $patch -p1 < ../patches/0005-apbuart-add-polling-callbacks-to-apbuart-driver.patch $patch -p1 < ../patches/0006-apbuart-add-support-for-virtual-KGDB-GRMON-channel.patch $patch -p1 < ../patches/0007-xsysace-Add-support-for-LEON-GRLIB-SoCs.patch $patch -p1 < ../patches/0008-usb-gadget-Add-UDC-driver-for-Aeroflex-Gaisler-GRUSB.patch $patch -p1 < ../patches/0009-greth-moved-TX-ring-cleaning-to-NAPI-rx-poll-func.patch $patch -p1 < ../patches/0010-sparc32-dma_alloc_coherent-must-honour-gfp-flags.patch $patch -p1 < ../patches/0011-sparc-Let-memset-return-the-address-argument.patch $patch -p1 < ../patches/0012-sparc-leon-Fix-race-condition-between-leon_cycles_of.patch $patch -p1 < ../patches/0013-sparc32-leon-Make-leon_dma_ops-available-when-CONFIG.patch $patch -p1 < ../patches/0014-sparc32-Implement-xchg-and-atomic_xchg-using-ATOMIC_.patch $patch -p1 < ../patches/0015-sparc32-leon-Align-ccall_info-to-prevent-unaligned-t.patch $patch -p1 < ../patches/0016-sparc32-destroy_context-and-switch_mm-needs-to-disab.patch $patch -p1 < ../patches/0017-sparc-optimize-MMU-fault-trap-entry.patch $patch -p1 < ../patches/0018-sparc-leon-workaround-for-MMU-errata.patch $patch -p1 < ../patches/0019-sparc-leon-Distinguish-between-IRQMP-and-IRQAMP-inte.patch

??? ?? ??? linux ?? ?? ???? ??? ????.

$cd .. $pwd /path/to/leon-linux-3.10-3.10.58-1.0.4 $cp config/config_up linux/.config

?? ??? ?? ???? ??? ??? ???.

$cp /path/to/leon-buildroot-2013.02-1.0.3/buildroot-git/output/rootfs.cpio /path/to/leon-linux-3.10-3.10.58-1.0.4/../dist/.rootfs.cpio

????? make ???? ??? ??? ???? ????.

$make build LINUX_TREE=linux

4) mklinuximg
????? mklinuximg? ??? LEON3? ?? ? ?? ???? ????.

$cd /path/to/mklinuximg-2.0.9 $./mklinuximg /path/to/leon-linux-3.10-3.10.58-1.0.4/linux/arch/sparc/boot/image image.dsu

? ???? ?? ?? ?? ??? ?? ??? ?????, ??? ?? ???? ??. ??? ?? ??? ???? ????? ??? ????, ?? ???? ??. (/path/to/mklinuximg-2.0.9/src/prom.c)

5) grmon? ??? LEON3 ??, ??? ??

$cd /path/to/grmon $./grmon -xilusb -nb -u grmon2> load /path/to/image.dsu 40000000 .text 4.2kB / 4.2kB [===============>] 100% 400010F0 .data 80B [===============>] 100% 40004000 .vmlinux 7.2MB / 7.2MB [===============>] 100% 4072B0C0 .startup_prom 39.6kB / 39.6kB [===============>] 100% Total size: 7.20MB (1.52Mbit/s) Entry point 0x40000000 Image /path/to/image.dsu loaded grmon2> run ... Welcome to Buildroot buildroot login: root #

[1] LEON3 Processor,
[2] Soft microprocessor, Wikipedia,
[3] Cobham Gaisler,
[4] ZedBoard,
[5] Xilinx University Program XUPV5-LX110T Development System, Xilinx,
[6] OpenSPARC Overview, Oracle,
[7] OpenSPARC, Wikipedia,
[8] ???, 20150721,
[9] LEON SPARC Mailing List,
[10] CoreX, Realtime Embedded,
[11] ZedBoard Zynq-7000 Development Board, Digilent,,400,1028&Prod=ZEDBOARD&CFID=13708886&CFTOKEN=bf9bf59caa35919f-A2243CAC-5056-0201-026AF17F0DA09716
[12] Zynq-7000 All Programmable SoC, Xilinx,
[13] What is ZYNQ? (Lesson 1), Microelectronic Systems Design Research Group,
[14] The Zynq Book,
[15] Zynq-7000 Boards, Kits, and Modules, Xilinx,
[16] ???, ZedBoard ?? ?? ?? ? ??? ??,
[17] Pete Johnson, An FPGA Tutorial using the ZedBoard,
[18] Training and Videos, ZedBoard,
[19] Sven Andersson, Zynq design from scratch. Part 1.,
[20] Download LEON/GRLIB, Cobham Gaisler,
[21] Downloads, Xilinx,
[22] Xilinx Design Tools: Installation and Licensing Guide, Xilinx,
[23] Cypress-USB2UART-Ver1.0G driver for Linux?, ZedBoard,
[24] ???, Kernel Compile and Multi-booting using Grub2,
[25] Digilent Adept, Digilent,
[26] leon3 with grmon on Xilinx zc702,
[27] Differences between ZedBoard and Xilinx Zynq-7000 SoC ZC702 Evaluation Kit, ZedBaord,
[28] GRMON Cannot Start,
[29] ???,

Categories: Planet FPGA

Altera (ALTR) update (July 23)

Distributed Feeds - July 23, 2015 - 6:30am
ALTERA shares will likely test support @ $46.71 (2011 high). Waiting for this level to enter this ma
Categories: Planet FPGA

Hackaday Prize Entry: An FPGA'd Propeller

Distributed Feeds - July 21, 2015 - 9:00pm

The Parallax Propeller is an exceptionally interesting chip that doesn’t get the love it deserves. It’s a 32-bit microcontroller with eight independent cores that are each powerful enough to do some real computation.  Around this time last year, the source for the Propeller was opened up and released under GPL 3.0, along with the mask ROM and an interpreter for the Propeller-specific language, Spin. This release is not only a great educational opportunity, but a marvelous occasion to build some really cool hardware as [antti.lukats] is doing with the Soft Propeller.

[antti]’s Soft Propeller is based on the Xilinx ZYNQ-7000, a System on Chip that combines a dual core ARM Cortex A9 with an FPGA with enough logic gates to become a Propeller. The board also has 16MB of Flash used for configuration and everything fits on a Propeller-compatible DIP 40 pinout. If you’ve ever wanted to play around with FPGAs and high-power ARM devices, this is the project for you.

[antti] already has the Propeller Verilog running on his board, and with just a bit more than 50% of the LUTs used, it might even be possible to fit the upcoming Propeller 2 on this chip. This build is just one small part of a much larger and more ambitious project: [antti] is working on a similar device with HDMI, USB, a MicroSD, and 32MB of DDR2 RAM. This will also be stuffed into a DIP40 format, making it an incredibly powerful system that’s just a bit larger than a stick of gum.

The 2015 Hackaday Prize is sponsored by:
Categories: Planet FPGA

Learn FPGAs in your Browser

Distributed Feeds - July 21, 2015 - 12:01am

FPGAs aren’t really programmed, they are configured. Most designers use Verilog or VHDL to describe the desired circuit configuration. Developers typically simulate these configurations before committing them to silicon (a good habit, especially if you ever graduate from FPGAs to ASICs where changes are very expensive). That simulation takes a lot of software you have to install and learn, right?

Not necessarily. You can do e-mail, word processing, and PCB layout in your browser. Why not FPGA design? The EDAPlayground website provides two editor views: one for your main “code” and another for the testbench (the simulation driver you use to test your design). You can even open multiple files, if you have a complex design.

Once you’ve entered your Verilog or VHDL (or picked one of many examples) you can run the simulation and see the result right in your browser. No software to install, and–outside of actually learning VHDL or Verilog–not much learning curve.

As [Strauburn], [combinatorylogic], and others commented on our recent post about a VHDL CPU, you can do a lot of learning without ever having your hands on real hardware. The web site gives you access to several different tools (useful if you want to see how your code will behave on different tools) and also many standard verification libraries. There are limited synthesis tools, but honestly, if you want to go to real hardware, you are going to want the vendor tools for the specific FPGA you are using.

As for learning the actual art of FPGA development, a quick search for Verilog tutorial or VHDL tutorial on the web or YouTube will get you started. Verilog is very C-like and VHDL is more like Ada, so choose accordingly. If you are craving VHDL, you can’t go wrong with Free Range Factory’s free book. For Verilog, this list will get you started.

Categories: Planet FPGA

Designing a CPU in VHDL for FPGAs: OMG.

Distributed Feeds - July 20, 2015 - 9:00am

If you’ve been thinking about playing around with FPGAs and/or are interested in CPU design, [Domipheus] has started a blog post series that you should check out. Normally we’d wait until the whole series is done to post about it, but it’s looking so good, that we thought we’d share it with you while it’s still in progress. So far, there are five parts.

minispartan6In Part One, [Domipheus] goes through his rationale and plans for the CPU. If you’re at all interested in following along, this post is a must-read. The summary, though, is that he’s aiming to make a stripped-down 16-bit processor on a Spartan 6+ FPGA with basic arithmetic and control flow, and write an assembler for it.

In Part Two, [Domipheus] goes over the nitty-gritty of getting VHDL code rendered and uploaded to the FPGA, and as an example builds up the CPU’s eight registers. If you’re new to FPGAs, pay special attention to the test bench code at the end of the post. Xilinx’s ISE package makes building a test suite for your FPGA code pretty easy, and given the eventual complexity of the system, it’s a great idea to have tests set up for each stage. Testing will be a recurring theme throughout the rest of the posts.

In Part Three, [Domipheus] works through his choices for the instruction set and starts writes up the instruction set decoder. In Part Four, we get to see an ALU and the jump commands are implemented. Part Five builds up a bare-bones control unit and connects the decoder, ALU, and registers together to do some math and count up.


We can’t wait for further installments. If you’re interested in this sort of thing, and are following [Domipheus]’s progress, be sure to let him know: we gotta keep him working.

Of course, this isn’t the first time anyone’s built a soft-CPU in an FPGA. (The OMG was added mostly to go along with the other TLAs.) Here’s a tiny one, a big one, and a bizarre one.

Categories: Planet FPGA

Why Intel Should Make a Challenging and Daring Bid for Micron

Distributed Feeds - July 17, 2015 - 8:15am

RAMMicron Technology Inc. (NASDAQ: MU) has had a solid week, with its shares bouncing handily on the heels of a reported $23 billion buyout offer from China’s Tsinghua Unigroup. There is just one problem, and that is not just that it may be a low-ball buyout offer. This proposed deal either will or should be blocked by U.S. regulators.

24/7 Wall St. has a thought here that should seriously be considered, and it comes with an up-front admission that the odds of success would seem to be very low. Intel Corp. (NASDAQ: INTC) should make a matching bid for Micron, with a promise of matching any such bid by Tsinghua Unigroup. Admittedly, U.S. and international regulatory bodies almost certainly would be all over Intel, trying to block this effort. That being said, there have not yet been enough loud voices against a proposed Chinese chip-making giant buying Micron.

Another complication comes up as well here. Intel has a working collaboration with Tsinghua Unigroup. Intel even invested roughly $1.5 billion for what was reported as a 20% stake in Tsinghua Unigroup. Intel may worry that reaching for Micron could harm its relationship with the Chinese outfit. Again, a merger of this magnitude is larger than mere share prices.

What is at stake here in a proposed acquisition of Micron by China is not just an issue of national pride. It is an issue of national security. Micron is U.S.-based and has much of its operations and many of its more than 30,000 employees here inside the United States. It claims to have the broadest memory solutions portfolio in the semiconductor industry, and it says that it holds over 20,000 patents. Micron makes critical DRAM and flash memory that is used in electronics, personal computers, internal systems and just about everything short of a basic toaster or wind-up alarm clock. That involves military, defense, law enforcement, government, corporate and consumer electronics alike.

ALSO READ: 10 Stocks to Own for the Next Decade

This proposal also would have an implication for Altera Corp. (NASDAQ: ALTR). Intel is trying to acquire this programmable logic devices-maker for $54 per share in a deal valued at some $16.7 billion. If the deal goes through, then Altera will become a unit of Intel, targeting existing and new customer sales. Intel signaled that it will continue Altera’s support and development of ARM-based and power management products.

As of July, Intel did not seem to have an assured regulatory clearance in its effort to acquire Altera. The company said that it expected a period of six to nine months to close the deal, and that was more than six weeks ago. If Altera is being acquired for $54, then the current price of $50.30 indicates that there is at least some regulatory risk to the deal closing.

Back to regulatory deal risk: The desire for Tsinghua Unigroup to buy up Micron almost has to be challenged by U.S. regulators. The Chinese would not allow a U.S. technology giant to come into China and buy up one of its top technology players. The Chinese might block a deal like that out of pride or security, and they have laws about what foreign companies can really own in China.

Tsinghua Unigroup is a Chinese company that is part of what is considered to be China’s top science university, Tsinghua University. To make an easy reference, let’s just call this the MIT-equivalent of China. And let’s not overlook the notion that China owns and controls state assets and entities. In late 2013, Tsinghua Unigroup made two acquisitions, of Spreadtrum and of RDA Microelectronics. Those were even larger than its market cap, so where did the funds come from? It is no secret at all that China wants to have its own dominant technology sector.

ALSO READ: AMD and Intel Are 2 Very Different Companies

Effectively, this would lead to a mostly state-run Chinese chipmaker taking over the top U.S. memory maker. The take of 24/7 Wall St. is that, despite nearly certain regulatory efforts immediately rallying against it, it would be better to have a U.S. monopoly of Intel-Micron (or even Intel-Micron-Altera) than it would be to have a state-owned Chinese chipmaker holding all our chips.

The Committee on Foreign Investment in the United States (CFIUS), the chair of which is the Secretary of the U.S. Treasury, reviews transactions that could result in control of a U.S. business by a foreign person or entity to determine the effect of such transactions on the national security of the United States. Again, think of all the flash memory and DRAM that is inside of national security equipment, on top of everything else.

Now let’s consider another issue here. Jack Lew, Treasury Secretary, just met with the Chinese delegation in Washington for the seventh meeting of the Strategic and Economic Dialogue, which is targeted at strengthening bilateral economic cooperation between the United States and China. Was this acquisition offer for Micron brought up? Did China get a nod? Did China get told to back off? Or did China point out how much Treasury debt it holds?

Needless to say, a Chinese company effectively owning the last chipmaker of DRAM and flash that is truly a U.S. operation should be considered something in which there are huge national security risks. CFIUS has a mixed history here, but if you consider that chips are used in nearly every single piece of defense and security equipment in the United States and abroad, then Micron’s ownership and domicile should matter. Still, a report in Forbes indicated that the proposed acquisition from China could be approved.

ALSO READ: Cisco’s Daring $10 Billion Investment in China

While some may have real concerns, there is no assurance that CFIUS would attempt to block the deal. It allowed IBM to sell its PC business to Lenovo, but it blocked the Chinese from buying 3Com. Still, Hewlett-Packard recently announced the sale of a majority stake in its Chinese server, storage and technology assets for $2.3 billion to Tsinghua University (Tsinghua Holdings) to become H3C. Bloomberg said at the time that was the first major U.S. technology company to pass control to local owners since the government stepped up restrictions on foreign firms.

If Intel owned Micron it would be one massive powerhouse, even far more than it already is. The antitrust concerns would be massive if Intel was able to control every aspect of the chip and memory sector. Still, if you only had two choices, would you rather have a Chinese state-run outfit owning a prized asset like Micron or would you rather let a U.S. giant keep all of Micron’s technology, most of its employees and its intellectual property (more than 20,000 patents) in America?

In 2013 Micron acquired Elpida, which also has ties to China, despite being based in Japan. Micron’s announcement in February of 2013 said that the Chinese Ministry of Commerce gave antitrust clearance for Micron’s pending acquisition of Elpida. Here is what stood out the most: China’s approval was the last remaining antitrust pre-merger clearance required for completion of the transaction.

This question over whether Micron should go to China or stay put does not even address the price of the proposed buyout. The $23 billion implied purchase price would be at $21.00 per share. This also would be a crushing deal for many Micron shareholders, and it would be a low-ball buyout, if history and analyst values matter at all.

ALSO READ: The 6 Most Shorted Nasdaq Stocks

Trading at $19.60 or so, Micron has a 52-week range of $17.14 to $36.59, and its consensus analyst price target is $29.64. That means the average of all analysts covering Micron, even after they largely lowered their targets, value Micron at almost $30 per share.

For those Americans who may be concerned that China would own or control a critical company like Micron, CFIUS can be contacted by email at [email protected] or by phone at (202) 622-1860.

Categories: Planet FPGA

ECE5760 Robot Navigation Using Sound Localization

Distributed Feeds - July 16, 2015 - 5:03pm
"The main idea behind this project was to construct a system on the Altera DE2 board that is capable of detecting the location of a sound source. We envisioned many purposes for such an instrument in gaming and other types of systems; however, to demonstrate our sound localizing capability in this project, we decided to use it for robot control."
Categories: Planet FPGA

Fiscal Year 2011 - 2014 - Earnings Per Share Basic - Semiconductor &amp; Related Devices - SIC 3674

Distributed Feeds - July 13, 2015 - 5:03am
Earnings Per Share Basic Ticker Symbol Company Name FY 2011 FY 2012 FY 2013 FY 2014 adi ANALOG DEVICES INC $2.90 $2.18 $2.19 $2.39 altr ALTERA CORP $2.39 $1.74 $1.37 $1.53 amat APPLIED MATERIALS INC /DE $1.46 $0.09 $0.21 $0.88 amd ADVANCED MICRO DEVICES INC $0.68 $-1.60 $-0.11 $-0.53 amkr AMKOR TECHNOLOGY INC $0.48 $0.26 $0.58 $0.56 aosl ALPHA & OMEGA SEMICONDUCTOR Ltd $1.61 $0.52 $-0.22 $-0.13 atml ATMEL CORP $0.69 $0.07 $-0.05 $0.08 avgo Avago Technologies LTD $2.25 $2.30 $2.23 $1.05 brcm BROADCOM CORP $1.72 $1.29 $0.74 $1.11 cree CREE INC $1.35 $0.39 $0.75 $1.03 cy CYPRESS SEMICONDUCTOR CORP /DE/ $1.02 $-0.16 $-0.32 $0.11 emkr EMCORE CORP $-1.54 $-1.66 $0.19 $0.16 entr ENTROPIC COMMUNICATIONS INC $0.31 $0.05 $-0.73 $-1.09 fnsr FINISAR CORP $1.10 $0.47 $-0.06 $1.16 fsl Freescale Semiconductor Ltd. $-1.82 $-0.41 $-0.81 $0.84 fslr FIRST SOLAR INC. $-0.46 $-1.11 $3.77 $3.97 idti INTEGRATED DEVICE TECHNOLOGY INC $0.45 $0.41 $-0.14 $0.59 intc INTEL CORP $2.46 $2.20 $1.94 $2.39 ipgp IPG PHOTONICS CORP $2.87 $3.02 $3.85 irf INTERNATIONAL RECTIFIER CORP /DE/ $2.35 $-0.79 $-1.28 $0.83 issi INTEGRATED SILICON SOLUTION INC $2.11 $-0.10 $0.62 $0.77 klic KULICKE & SOFFA INDUSTRIES INC $1.77 $2.17 $0.79 $0.82 kopn KOPIN CORP $0.05 $-0.29 $-0.08 $-0.45 lltc LINEAR TECHNOLOGY CORP /CA/ $2.52 $1.71 $1.72 – lscc LATTICE SEMICONDUCTOR CORP $0.66 $-0.25 $0.19 $0.41 mchp MICROCHIP TECHNOLOGY INC $2.24 $1.76 $0.65 $1.99 mcrl MICREL INC $0.55 $0.21 $0.31 $0.24 mrvc MRV COMMUNICATIONS INC $-0.87 $0.72 $-0.91 – mscc MICROSEMI CORP $0.66 $-0.35 $0.49 $0.25 mu MICRON TECHNOLOGY INC $0.17 $-1.04 $1.16 $2.87 mxim MAXIM INTEGRATED PRODUCTS INC $1.65 $1.32 $1.56 $1.25 mxl MAXLINEAR INC $-0.68 $-0.40 $-0.37 $-0.19 nvda NVIDIA CORP $0.44 $0.96 $0.91 $0.75 onnn ON SEMICONDUCTOR CORP $0.03 $-0.20 $0.34 $0.43 powi POWER INTEGRATIONS INC $1.20 $-1.20 $1.95 $1.99 psmi PEREGRINE SEMICONDUCTOR CORP $-3.57 $0.19 $-0.13 – pxlw PIXELWORKS INC $-0.40 $-0.31 – – quik QUICKLOGIC CORPORATION $-0.21 $-0.29 $-0.27 $-0.23 rfmd RF MICRO DEVICES INC $0.46 $- $-0.19 $0.18 rmbs RAMBUS INC – $-1.21 $-0.30 $0.23 semi SunEdison Semiconductor Ltd – $2.92 $-1.39 $-2.17 smtc SEMTECH CORP $1.16 $1.37 $0.64 $-2.44 spir SPIRE Corp $-0.18 $-0.22 $-0.92 – spwr SUNPOWER CORP $-6.28 $-3.01 $0.79 $1.91 spwra SUNPOWER CORP $-6.28 $-3.01 $0.79 – sune SUNEDISON INC. $-6.68 $-0.76 $-2.46 $-4.40 swks SKYWORKS SOLUTIONS INC. – $1.09 $1.48 $2.44 tqnt TRIQUINT SEMICONDUCTOR INC $0.29 $-0.16 $-0.24 – tsra TESSERA TECHNOLOGIES INC $-0.38 $-0.58 $-3.48 $3.23 txn TEXAS INSTRUMENTS INC $1.91 $1.53 $1.94 $2.61 xlnx XILINX INC $2.43 $2.01 $1.86 $2.37
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