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Xilinx and Agilent DDR4 at 2400 Mb/s for JEDEC Compliance

Distributed Feeds - April 18, 2014 - 6:52am

Thanks to Xilinx for this video clip featuring my colleague Ai-Lee Grumbine demonstrating our DDR4 compliance app on their demo board with the UltraScale 2400Mb/s DDR4 controller. (Please be patient: the video stream takes a few seconds to buffer.)

Categories: Planet FPGA

Xilinx Introduces SDNet & 'Softly' Defined Networks | EE Times

Distributed Feeds - April 17, 2014 - 6:59pm
Image representing Xilinx as depicted in Crunc...

Image via CrunchBase

It’s not often that you see something that makes you think “this is a game changer.” The introduction of logic synthesis circa 1990 was one such event; today’s introduction of SDNet from Xilinx may well be another.

via Xilinx Introduces SDNet & ‘Softly’ Defined Networks | EE Times.

Cisco has used different RISC chips over the years as its network processors. Both in it’s network closet switches and the core router chassis. First generation was based on the venerable MIPS processor, then subsequently they migrated to PowerPC, both for power reduced processing but also network optimized cpus. Cisco’s engineers would accommodate changes in function by releasing new version of the IOS. Or they would release new line cards for the big multi-slot router chassis. Between software and hardware releases they would cover the whole spectrum of wired, wireless, optical networking. It was a rich mix of what could be done.

Enter now the possibility of not just Software Defined Networking (kind of like using Virtual Machines instead of physical switches), but software defined firmware/hardware. FPGAs (field programmable gate arrays) are the computing world’s reconfigurable processor. So instead of provisioning a fixed network processor, and virtualizing on top of that to gain the software defined network, what if you could work the problem from both ends? Reconfigure the software AND the network processor. That’s what Xilinx is proposing with this announcement of SDNet. The prime example given in this announcement is the line card that would slot into a a large router chassis (some Cisco gear comes with 13 slots). If you had just a bunch of ports, let’s say RJ-45 facing outward, what then happens on the inside via the software/hardware reconfigurability would astound you. You want Fibre Channel over Ethernet? You want 10Gbit? You want SIP traffic only? You don’t buy a line card per application because it’s set in stone what the function is. You tell the SDNet compiler these are the inputs, these are the outputs, please optimize the functions and reconfigure the firmware as needed.

Once programmed, that line card does what you tell it to do. It can inspect packets, it could act as a firewall, it could prioritize traffic, shape bandwidth or just simple route things as fast as it could possibly go. Doesn’t matter what signals are running over what pins, as long as it knows it’s RJ-45 connectors, it will do the rest. Amazing when you think about it that way.

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Categories: Planet FPGA

Spartan 6 – FPGA Based Bus Pirate

Distributed Feeds - April 16, 2014 - 8:20am
"A FPGA based design with a soft CPU and USB device interface implemented in Verilog. A small USB stack implements a virtual serial port over USB, but could be extended to support other class drivers such as Audio or HID. This board is form factor compatible with the Bus Pirate v3.5 case"
Categories: Planet FPGA

BeagleBone Black and FPGA Driven LED Wall

Distributed Feeds - April 11, 2014 - 4:00am

LED Wall


This is 6,144 RGB LEDs being controlled by a BeagleBone Black and a FPGA. This gives the display 12 bit color and a refresh rate of 200 Hz. [Glen]‘s 6 panel LED wall uses the BeagleBone Black to generate the image, and the LogiBone FPGA board for high speed IO.

[Glen] started off with a single 32 x 32 RGB LED panel, and wrote a detailed tutorial on how that build works. The LED panels used for this project have built in drivers, but they cannot do PWM. To control color, the entire panel must be updated at high speed.

The BeagleBone’s IO isn’t fast enough for this, so a Xilinx Spartan 6 LX9 FPGA takes care of the high speed signaling. The image is loaded into the FPGA’s Block RAM by the BeagleBone, and the FPGA takes care of the rest. The LogiBone maps the FPGA’s address space into the CPU’s address space, which allows for high speed transfers.

If you want to drive this many LEDs, you’ll need to look beyond the Arduino. [Glen]‘s work provides a great starting point, and all of the source is available on Github.

[Thanks to Jonathan for the tip]

Categories: Planet FPGA

tPad Embedded System: the 2048 game + Draw Picture

Distributed Feeds - April 10, 2014 - 10:11pm

This time, we had an advanced version of FPGA project (comparing to Color Piano), which involving touch panel, gravity sensor and VGA screen.  It was also an embedded system design, that could had more functions and more adaptivity  than implying the hardware alone.

The system was first designed with only the “start” screen and the “touch-draw” function last year. Then we added the fun game “2048”, to make it more fun.

  • The old tPad project.

We had this tPad project one year ago in the advance VLSI design class. The we tried embedded system for the following reasons:

  1. We could have software in the project, like programming in C, other than Verilog alone.
  2. The hardware design could be separated with the software function.
  3. Highly adaptivity and easier to add more functions.

We started building the hardware frame by using SPOC builder from the Quartus II. Adding the CPU, JTAG, CFI Flash, SDRAM, PLL, ADXL345, I2C and the LCD screen and other components.

Then we added a Power Manage Unit in the hardware to realize the function of “saving power”, which was turning off the screen if the screen was not touched for 10 seconds (we made it 3 seconds in the video demonstration).

Luckily the Altera had provided the drivers for all the hardware components, and we could directly use those drivers.

We realized the “draw” function by collecting the dots that we touched on the screen. And you could choose different colors and clear the previous screen. You could also clear the screen by shaking it.

The glitches in the video are caused by 2 major reasons: 1. The screen is a resistive touch screen, it is less accurate than the capacitance touch screen. 2. We lowered the frequency of getting the position of dots. So when I moved quickly on the screen, the dots were more “discrete”

  • The 2048 game

This presentation was the 2048 game alone.

When we were wrapping the previous projects, the fun game 2048 ( ) was launched,  and we started the idea of making it into out tPad system.  We chose the gravity sensor as the input instead of  arrow keys. You could also choose to restart the game by touch the “Clear” button.

  • Integrated Together

From this “integrated” system that we can choose which the sub program to run and return to the start menu, as the video in the beginning.

Categories: Planet FPGA

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