World's 1st FPGA/CPLD Portal

It's 4:45AM. Charles hits "snooze" one last time on his alarm clock. He can wait another 8 minutes before trying to really wake up for his 5AM conference call with Europe. His status report is 80% finished on his laptop, which waits in "hibernate" by his bed. His smartphone is on his nightstand, next to his bluetooth headset. He tells himself he's pretty much ready for the meeting. 4:53AM - the alarm beeps again and Charles forces his eyelids apart, rolls out of bed and stumbles down the hallway to the kitchen. The espresso machine is already warmed up. He drops in a coffee pod, places a cup below the spout, and presses the "Lungo" button. He wants the extra kick to keep him awake through his call. The 60-second espresso pull feels like an eternity and he bats his eyes into focus as the dark brown liquid slowly lightens. Finally, the machine clicks to a stop and he trundles back down the hall toward his bed, cuddling the warm mug with both hands.....

Reconfigurable end systems mean test challenges that are best served by reconfigurable instruments. NI's Eric Starkloff covers the role of FPGAs in such test scenarios, as well as how reconfigurable test can reduce the time and cost of test.

In SIGPROC signal processing of information, such as filtration, detection, predicting of the signal,etc., should use the electric-wave filter, the digital filter is the most popular method in digital signal processing, the commonly used digital filter has long unit impulse response (IIR) limitlessly Electric-wave filter and unit impulse response of the finite length (FIR) Two kinds of electric-wave filters. For employing the artificer, because rate of development and efficiency are expected very much, can not understand associated optimization technique of digital filter in an all-round way in short term, the energy needing to spend a lot of money can make the electric-wave filter designed prone to more excellently in the speed, utilization of resources, characteristic. And adopt IP kernel debuggedding needs buying from Altera Company. This literary grace uses fpga design method based on DSP Builder, take realization of an 16 low-pass steps FIR electric-wave filter as examples, module document design of module file of top level of electric-wave filter and A/D through producing, proved that utilizes the digital trap circuit that is designed of this method to work correctly reliably in uniting NC-EDA-2000C experiment box of the star science and technology, can meet the designing requirement.

The number of 1 FIR electric-wave filter is designed

1.1 Designing requirement

Actually a linearity of adopting the limited precision algorithm and realizing of digital filter is not a discrete ststem of time varying, to design step as, confirm performance index their depending upon need first it, design a system function H (z) Approach the required technical indicator, adopt the limited precision algorithm to realize finally. This systematic one designs index as: Design one and 16 stepses of low-pass FIR electric-wave filters, the sampling frequency Fs to the analog signal is 48KHz, require the alpha cut frequency Fc of the signal =10.8kHz, the input sequence is that the width is 9 (the widest location is the sign bit) .

1.2 The parameter of FIR electric-wave filter is chosen

While designing the digital filter of frequency selectivity, usually hope that there can be the range of approximately invariable Frequency Response FR, and try hard to reduce the inner phase distortion of the band pass, the slope is the simple time delay inside the country when the linear phase of the integer is correspondent to, he can reduce the phase distortion to the minimum intensity [2 ] in the frequency domain, the special tool box of filter design that offers with Matlab –Design the electric-wave filter in FDAtool emulation, FIR electric-wave filter amplitude/frequency characteristic of meeting the demands, as shown in Fig. 1.

DSP Builder of 2 digital filters designs

2.1 DSP Builder introduction

DSP Builer is a digital signal processing (DSP) that Altera puts out Developing instrument, he is in Quartus II fpga design environment Matlab and Simulink DSP of integrated Mathworks develop the software [3 ]. As to DSP Builder, including the modeling of DSP system, system level simulation, design model are to conversion, RTL of VHDL hardware description language code (Register Transfer Level, logic synthesis) Grades of the intersection of function and emulation test, compile adapt and the intersection of overall arrangement and routing, the intersection of sequence and real time simulation until to the intersection of DSP and the intersection of goal and programming disposition of device, nearly can develop procedure the intersection of developing instrument and Matlab/Simulink in top level with finish in the an environment while being whole.

2.2 FIR electric-wave filter algorithm model building

According to FIR electric-wave filter principle, can make use of FPGA to realize FIR smoothing circuit, DSP Builder designs the first step in the procedure to be to design input in Matlab/Simulink, namely set up a MDL model file in Simulink environment of Matlab, transfer the figure module in Altera DSP Builder and miscellaneous Simulink storehouse by means of figure, commit system level or algorithm level, design block diagram ‘ Or Simulink modeling) .

2.3 On the basis of the system level simulation of DSP Builder

It is f1 respectively that the input signal adopts the frequency =8KHz and f2 =Two sine signals of 16KHz are superposed, the artificial waveform among them is shown as in Fig. 2, find out from the simulation result of FIR smoothing circuit, output and basically turn into a unifrequent sine signal after the coherent wave filter of the input signal, have so far finished model emulation.

Realization of the digital filter of FPGA of 3 group

3.1 Use Modelsim to carry on function emulation

The emulation carried on in DSP Builder belongs to system authentication properties, it is the emulation done on MDL file, have not carried on emulation to VHDL code produced. In fact, produce VHDL to describe it is RTL grade, it is structural to be for the concrete hardware, there may be software between these two and understand the difference on, VHDL code after changing realizes that may not totally conform with the situation of MDL model description, this needs to carry on function emulation to the RTL grade VHDL code that is produced.

We make use of Modelsim to carry on function emulation to VHDL code produced. It is an analog form to set up the input/output signal, the artificial waveform shown in Fig. 3 appears, can see this is basically identical with simulation result in Simulink. Can under the environment of Quartus II hardware design [4 ].

3.2 Realize FIR electric-wave filter in FPGA device

What the digital filter realized by FPGA is dealt with is digital signal, in real application, will pay sampling and quantize to the analog signal with A/D converter at first. Traditional most methods are finished with CPU or one-chip computer, the shortcoming is that control cycle is long, slow. And it is that one kind has been already simple and reliable to make use of synchronous sequence state machine to control A/D to sample, can improve and sample the periodic and effectual method notably.

Design this state machine and change into on request through VHDL language Quartus II environment. Bsf file; Open Quartus II item file fir.qpf and fir.vhd that DSP Builder sets up and change into the corresponding one. Bsf file, therefore can get the module designed correspondingly, as shown in Fig. 4, two pieces of module of call set up new top level schematic diagram file, through sequence emulation, appoint the base pin of the device in the software environment, compile, download in EP1K10TC100-3 device of the experiment box finally.

4 concludes the speech

Produce the sine signals of two pieces of different frequency required with the signal generator, see that filters the result for the future on the all right ondoscope, while needing to design different smoothing circuit, only revising the model file of the electric-wave filter can be realized. It is obvious when not carrying on development of digital filter with FPGA, adopt DSP Builder, design the practical filtering system as design tool swiftly, reliably.

High clear TV (HDTV) It is the liquid crystal display (LCD) Technical newest application, it needs more high definition than standard LCD technology, and the data rate and power consumption have increased. Because of raising the data rate, so the high-speed sport video needs specialized image manipulation algorithm. These algorithms can be in the field programmable gate array (FPGA) China realize, digital the intersection of video signal and accurate conversion, mapping at the display panel.

LCD designer adopts FPGA, the reconfiguration image manipulation algorithm that can be flexible, on the same hardware platform, make LCD of different size in all products can meet the increasing data rate. Especially on the digital consumption market, FPGA can offer most valid cost, characteristic and flexibility equilibrium scheme for digital television and display. LCD TV manufacturers can fully utilize FPGA technology, realize the products appear on the market in time, make the products enter the retail channel rapidly, occupy the most favorable position in the competition.

A LCD system can launch designing around FPGA, among them run FPGA coprocessor of the real-time embedded operating system controls a display equipment. The designer not only can adopt FPGA in the expicity central control box but also can adopt FPGA in dealing with the communications link specializedly. For example, FPGA is very suitable for realizing some available display functions, deals with real-time zooming to the video flowing.

FPGA of new most generation contains the hardware encoding digital signal processing (DSP) that is optimized Module, make up the basic cells of video and image manipulation. DSP module walk abreast at a high speed handling capacity suitable for image manipulation,etc. need big the intersection of data and DSP application of throughput.

The most frequently used DSP function includes finite impulse response (FIR) Filter, complicated FIR filter and Fu set up leaf vary (FFT) fast , discrete cosine transform (DCT) And the relevant algorithm,etc.. These functions are HDTV and other complicated LCD applied basic construction module.

Use FPGA technology to also have another advantage in LCD system – -Design numerous programming in the all right whole life cycle of goods in process of system designer, this key characteristic makes the designer redesign the overall system, can be increasing the new function of the products in the model change constantly.

Overcome the new technology of HDTV obstacle

HDTV is becoming the commercial video mainstream, the leading firm in the industry introduces into specialized technology and promotes LCD to enter HDTV application.

National semiconductor (National Semiconductor) Have introduced the differentiating signal of the low-voltage (LVDS) To reduce LCD interface power consumption and electromagnetic disturbance (EMI) at a high speed . Flat panel display device (FPD) It is in LCD HDTV and monitor platform that the national semiconductor defines, because of the interlinking of LVDS between host computer faceplate and display panel.

The national semiconductor has also defined the low excursion differentiating signal (RSDS) The standard, is used mainly in the definition in VGA and UXGA (expand the patterned array rapidly) During display application. Instrument of Dezhou (Texas Instruments) Also introduced the similar interface standard – -Mini-LVDS, its purpose also reduces power consumption and EMI. Interlinkage of level (Flat Link) It is in LCD HDTV and monitor platform that TI defines, because of the interlinking of LVDS between host computer faceplate and display panel. Mini-LVDS interface standard is basically identical with RSDS, but mini-LVDS has adopted the collimated output clock of the centre in order to accord with AC regular requirement. This interface and FPD are interlinked similarly, is mainly adopted by LG, Philips and Thomson, applies to their LCD HDTV products. Because consumers favor in the bigger TV display unit more and more, the designer carries on circuit board and Layout Design, while realizing the signal completeness, still there is certain limitation in present interfacing. A kind of latest interfacing which is named PPDS that national semiconductor has been developed, the purpose lies in realizing bigger LCD reveals. Table 1 has summarized all kinds of display panel technology. Fig. 1 is a typical figure LCD TV module block diagram. The intersection of tuner and module can satellite, the intersection of ground and wireless or cable demodulator, it is thereafter MPEG2 demodulator. Besides signal from figure TV tuner, a typical LCD TV can also offer DVI (digital visual interface) , HDMI (high clear multimedia interface) , input interfaces of external video such as simulation RGB, CVBS, S-video and TV signal component,etc..

LCD HDTV monitor can deal with various video input signal formats. It can map to directly some form in display unit,but reconditioning necessaries miscellaneous could displays accurate.

The core of LCD HDTV is its image manipulation and regular control module. The image processing module usually includes such functions as converter of rate of scanning, frame speed converter, color demoder, movement surveying, scaler are conciliated and interleaved. Fig. 2 is a typical LCD TV interface module block diagram.

LCD color response mainly depends on the color capacity, its response time is relatively slow, it is a image manipulation algorithm (but the weird signal of the destination vision) Difficult point in the design. The design flexibility of FPGA is offered the advantage that the products appear on the market in time, makes the designer redesign algorithms in the device, needn’t carry on the planning of programming again.

Display unit manufacturer add own private algorithm into products, realize very colored and raising sporting and revealing the characteristic, thus can lead the rival. LCD very colored video characteristic that two kinds of specialized video accentuation methods emerge.

The first kind of method is the time jitter, within certain time cycle, quick switchover the on-off state of the picture element, produce the real grey level of different colors. The second kind of method is that the space shakes, produce certain amounts of intensity grades of color. The space will produce the space noise or error to spread while shaking; Need further filtering and tight alignment to dispel this kind of noise.

Conclusion

LCD was used mainly in more stable computer data text and graphic display in the past, but is used for revealing the video signal of rapid movement on bigger display panel now, this specialized image manipulation algorithm needed and be able to be realized in FPGA. It can be on the standard hardware platform that LCD designer adopts FPGA technology, reconfigures these algorithms according to the faceplate size, thus reduce the Manufacturing cost and accelerate the products and appear on the market.

Main manufacturers introduce many kinds of technology, mini-LVDS such as low-voltage differentiating signal and low excursion differentiating signal and Dezhou instrument of the national semiconductor, overcome power consumption and electromagnetic obstacle, make LCD can be applied to HDTV commercial field.

FPGA flexible in use pays dynamic image manipulation, adopts the new technology to overcome HDTV power consumption and EMI obstacle, the designer can further bring LCD into commercial TV of the front and reveal the application.

FPGA-based prototyping is probably the most popular and effective method for debugging and verifying complex designs at a reasonable speed. FPGAs can emulate your hardware design - usually at very near actual operating frequencies. As a result, you can run tests that you could not even contemplate with methods like simulation - including gathering real-wold stimulus from sensors, cameras, or other high-bandwidth hardware. None of this is new. Unfortunately, another thing that isn’t new is that, despite a decade or two of refinement, FPGA-based prototypes are still unbelievably difficult and complex to get working in the first place, and they can be exceedingly tricky to use and understand properly. Starting with a nice, clean, HDL-based design that seems to work well (albeit slowly) in your favorite simulator, one might expect it to be a semi-trivial matter to get that same design up and running on that nice new FPGA prototyping board (or box) that you bought (or built). Wrong-O....

The car amusement electron promotes the fast development of function and capacity, impels the designer to consider on the characteristic, cost and flexibility synthetically. With other car electrons ” >Electronic fields of the car are different, it is highly visual that the multimedia figure is employed, its demand is changeable, in many situations not even set up the standard yet. Designer needs one car can offer most flexible, the characteristic is best and solution that the cost is controllable. Programmable logic, especially field programmable gate array (FPGA) It is such a solution.

In the past, application-specific integrated circuit (ASIC) Can offer the chip scheme with better cost-effective to manufacturer, so, the car figure is applied to the semi-conductive respect to generally choose ASIC. But, ASIC development cost soaring constantly, it may indicate ASIC rules the concluding of the times in the automobile market to reduce the improvement of price of batch, requirement and functional complexity for appearing on the market fast. The top car supplier is looking for a kind of design platform that has cost-effective most, its strong function and flexibility can meet the demand for the increasingly complicated car number system.

Specialized standardized product (ASSP) It is a kind of alternative scheme of ASIC on car and consumption market. The main advantage of this kind of product lies in the low cost. However, ASSP has implicit cost, ASSP substantially as looking for various with suitable function, but needn’t add external logic, software, other ASIC or ASSP. Moreover one that is with demand to change, design, may need ASSP while being early, design once going into operation, no longer adopt ASSP.

FPGA can shorten the development time of project notably, reduces many chips and repeats the use cost, become the powerful and flexible solution that the car figure substitutes ASIC and ASSP while employing. ASSP may lose the required function, there is ASIC with designing revising the risk that must be made again, and FPGA can carry on programming, and programme again depending upon need in the course of designing, the ones that realized more fast are prototyping, accelerate the products and appear on the market. If the demand was changed, even the device has already come into operation in the vehicle, FPGA can be upgraded live too. FPGA does not have ASIC sheet (NRE) in advance Cost and minimum order amount question, there is no ASSP associated potential cost problem either, it is that the system design has a choice of cost-effective most. Moreover, the ability that FPGA can be reused on the common hardware platform seems very important, make the designer produce different systems, relying on a basic design can support many kinds of functions, thus reduce the Manufacturing cost.

FPGA reference design promotes the car figure technology

Information amusement employs the increasingly complicated graphics capability of the requirement. This kind of treatment can be realized in advanced processor and DSP, but the cost is extremely high cost, complexity and power consumption. Can add FPGA into system to reduce the total cost, complexity of the graphic system, and performance requirements. Fig. 1 shows as a canonial figure reference design, this design bears the weight of video input, cover the expicity other pictures on LCD screen.

Fig. 1: Adopt the car figure control systems of FPGA and host computer processor

This reference design is in the Altera Cyclone&-#; 8482; Has realized a video load module and LCD graphics controller in FPGA, while showing the required low cost of automobile market is employed, strong function and flexibility that FPGA has. On running and developing the board in Altera Nios II embedded processor in reference design, and added the module used for realizing the camera / video input, exporting and revealing the driving circuit.

The video load module includes a forward end camera interface and is used in the spatial switching of color, IP adjusted and zoomed, and video memory interface. LCD reveals the interface includes controlling IP function of different between layer and semitransparent result between the visions. The control module of these import and exports is the constituent elements of Altera SOPC Builder systems, this system is used for carrying on the seamless link of all IP module. OpenGL-E graphic base subset runs in the host computer CPU. This storehouse is offered all functions of dealing with and signifying the bit map, the frame buffers visiting and graphic primitive drawing.

While perspecting, rotating, drawing straight line, polygon, lamination operating and similar task, these will take up a large amount of calculation to employ to expand the figure, so, may need a host computer CPU with very strong function to realize OpenGL graphic base. FPGA can unload the algorithm function usually consuming a large number of CPU characteristics in the host computer CPU as a coprocessor framework.

Fig. 2: There is figure control system that the hardware accelerates the coprocessor

Fig. 2 showed and added the embodiment of the graphics acceleration coprocessor in consulting the design system. This coprocessor can bear the weight of many kinds of algorithms, for instance:

Image transfer of bit block (BLIT) such as direct blit, drawn blit, transparent, a pair of linear filtering, every picture element alpha, colouring, resisting the sawtooth and dealing with Operation Draw, round angle, rescinded angle, alpha gradient, picture edge fog (fuzzification) in arbitrary width straight line , alpha gradient, picture edge fog (fuzzification) that polygons such as triangle pattern, quadrangle,etc. are drawn Round, ellipse and conical section section are drawn Produce the quadratic sum B three times

A complete logic prototyping system, the DN2076k10 employs seven Virtex-6 FPGAs and can emulate up to 37 million ASIC gates at clock speeds to 700 MHz.

1,Foreword

Alpha magnetic spectrometer (Alpha Magnetic Spectrometer, AMS) What the laboratory is led by the doctor in Ding Zhao is by large-scale international collaborative projects that more than 300 scientists participate in altogether of U.S.A., Russia, Germany, France, 16 medium-sized countries or regions. It is the only large-scale physical experiment on the international space station, human the first time to measure the experiment with electric atomic nucleus particle of the high-energy in the space closely. Its purpose is for looking for antimatter constituent universe and source of the dark material and collinear source of measurement universe.

But will receive the attack of the energetic particle too to the space electronic system of AMS experiment, cause the content of the memorizer to change, rewrite the logic state of the semi-conductive storage device, lead to the fact memory cell is turned over among logic ‘ 0 ‘ and ‘ 1 ‘, make the key data stored make mistakes, the control procedure runs and flies etc.. This, to AMS experimental system, it is a question that can’t be ignored. So, we adopt dual BCH(31, 16) Yard, can correct three random errors, this kind of error correcting code information does not need storing, does not need to feedback, the real-time nature is good.

2,Principle of the compiled code

It is a question presented to be electronic to the space, we carry on error checking and correction, its basic thought is a redundant code by way of joining differently in certain rule in the information block, in order to rely on surplus supervision yard or check-up yard to find or correct the mistake automatically when information is read out.

2.1 Code

The code is simpler, dual BCH(31, 16) It is GF(25) The linear block code on the land, the most significant position m of the binary scale among them =5,Total information long n =2m-1 =31,Check-up figure k =15,But the error correction bit counts t =3,Generating polynomial g(x) For:

2.2 Decipher

The decode procedure is more complicated, include 1) Ask the adjoint polynomial, 2) The computing circuit of coefficient, 3) The computing circuit of wrong position, among them the most key one is the third step, such as Fig. 1. Here suppose the intersection of data and wrong 3 that receive, the 28th, 20, 17 deflect 0/ 1, namely

(1)Ask the adjoint polynomial

According to the relation between the minimum multinomials of generating polynomial and ai, use & phi; i(x) Remove the received polynomial R(x) And receive syndrome’s weight, namely,

1 2

A foreword

ARM(Advanced RISC Machines) Can already be regarded as a company. Can it thinks to be referred to as to a kind of microprocessor, can also be regarded as a technology. The microprocessor based on ARM technology should be by nearly occupying the market share above the RISC microprocessor 75% of the 32-bit microcomputer, ARM technology is penetrating to all respects [1 ] of people’s life progressively. Up till now, ARM microprocessor and technology have already been applied to each field extensively, including industry controlled field, network application, consumption electronic product, imaging and safe products,etc..

FPGA(Field Programmable Gate Array) It is a kind of high density FPLD, its logic function is to design the data file produced to dispose to the static disposition data storage (SRAM) of the device inside through one Come to realize. FPGA has repeatable programming, can be flexible to realize various logic functions.

FPGA based on SRAM craft has volatility. Their internal configuration data are easy to lose after the systematic power down, so need to connect ROM and keeping their configuration data, systematic power up must another the intersection of configuration data and ability normal operation. Two kinds of schemes can be realized at present, one uses dedicated PROM, with Xilinx Company FPGA, XCFxx series PROM is the example, can offer the disposition sequence of FPGA, in the automatic configuration data SRAM to FPGA with year PROM at the time of power up; Another kind of contain system of microprocessor China adopts other nonvolatile memories such as E2PROM, Flash to store the configuration data, the disposition sequence of simulation FPGA of the microprocessor puts the data in ROM into FPGA. Compared with first kind of scheme, this scheme saves the cost, narrows the systematic volume. Suitable for the harsh system that required to the cost and volume.

In the walkie fictitious instrument design, use embedded system and FPGA to realize the system function. The embedded microprocessor adopts the ARM7TDMI series processor S3C44BOX of Samsung Company: FPGA adopts Spartan-3E series XC3S100E of Xilinx Company, adopts S3C44BOX to finish the disposition to XC3S100E. Have made the good result.

2 is from one bunch of principles disposed

2.1 disposes the principle from bunch

The Spartan-3E series FPGA products of Xilinx Company adopt 90 nm technological 2.5 V low-voltage FPGA devices One, have high performance, low power consumption, characteristic that can be written many times. XC3S100E is a style in Spartan-3E series FPGA, the total gate count is up to 100,000 doors, can adopt from bunch, main fact bunch, dispose it from and, mode of main fact and, JTAG,etc. [2 ]. XC3S100E is and as follows from one bunch of main pin functions with relevant Configuration Mode:

M[2: 0]: Dispose the mode selection. M2, M1, M0 connect and pull upward the resistance, namely M [2: 0]: It is from the string pattern at 111 o’clock;

CCLK: Dispose the clock, the microprocessor offers the clock source, and the rising edge is effective:

DIN: Dispose the data entry serially:

DOUT: Serial data output, are used in the chrysanthemum chain to dispose:

PROG_B: The low level is asynchronous to reset the logic within FPGA, internal configurated: After Memory totally resets, this pin points out the high level.

When for being high pin this, could dispose FPGA:

INIT_B: From the low level until high level jump transfer, sample the Configuration Mode, namely M [2: 0]Worth confirm Direction; If disposes the mistake in the configuration procedure, INIT_B will present the low level;

DONE: As the low level while resetting. If dispose success, it is the high level.

2.2 microprocessors dispose from bunch: Sequence of FPGA

The configuration procedure of FPGA is as follows:

Behind the systematic power up, draw PROG_B low in order to reset logic reconfigure FPGA inside the FPGA, reset behind the internal logic fully (invite 100& mu; s),Put PROG_ high.

INIT_B is the low level, after PROG_B draws high to keep 300 ns, FPGA puts INIT_B high. By the low twinkling of an eye to high jump transfer, sample the Configuration Mode M [2 in INIT_B: 0]. This system adopts from one bunch of Configuration Modes.

After FPGA samples the Configuration Mode, the microprocessor can dispose clock CCLK and data to FPGA, in rising edge of CCLK, transmit data to DIN, data byte send low order first, send the high position and then. If makes a mistake in the configuration procedure, then INIT_B is the low level.

All data transmission of disposition is finished, CRC check-up is errorless. Then DONE is the high level, otherwise the low level.

DONE is the high level, FPGA releases the overall tristate (GTS) ,Activate I/O pin, release all set to reset (GSR) And the overall situation is written can enable (GWE) Effective, begin to carry out the logic of the disposing area.

The microprocessor is shown as in Fig. 1 from a bunch of sequence of disposing FPGA.

2.3 Generation method of the configuration file

Exploit the developing instrument ISE8.1 offered by Xilinx Company, can produce the programming file after synthesizing, shining upon, overall arrangement routing, the programming file contains. Bit. Bin. Mcs. Tek. Forms such as hex,etc.. Among them. Bit form is used in JTAG download, some other kinds of forms are used in the programming of specialized PROM. Produce according to the method to produce specialized PROM programming file at first. Bin file. These. Bin file is converted to the memory form of ASC? one yard of files, and separate with the comma between each byte. In leave one the intersection of head and array config_data_array of file of system program in configuration data this and then ‘ ], as a part of source code of system program, and compile with other procedures.

3 hardware design

The kernel of embedded microprocessor S3C44BOX built-in ARM7TDMI, have integrated the abundant peripheral function module, internal 8 kB Cache has improved the characteristic greatly. S3C44BOX can visit the address space of 256MB, the maximum operating frequency reaches 66 MHz. Adopt 4 MB Flash as the programm store, can be use for depositing the code that the system ran. XC3S100E configurator and configuration file firm to keep therein from bunch, Flash this support low-voltage (1.65 V- 3.3 V) Write operation. SDRAM of 8 MB is a operation space of the procedure, the code running in Flash directly, but the speed is very slow. Usually move the code in Flash to SDRAM. S3C44BOX and XC3S100E mainly connect through PROG_B, INIT_B, DONE, CCLK, 5 sticks of signal line of DIN, as shown in Fig. 2. Among them VCC33 represents 3.3 V, VCC25 represents 2.5 V.

4 software design

The procedure of software design is shown as in Fig. 3. Disposing the programming of the software should guarantee ARM totally according to the sequential working of disposing the signal, key issue

It is the sequence of adopting simulation DIN, CCLK, DONE, INIT_B, PROG_B of common I/O GPF0 once, GPF1, GPF2, GPF3, GPF4 of S3C44BOX.

In S3C44BOX, most pins are multi-functional pins, can be chosen the corresponding pin function through the port configuration register.

Take port F as examples, the control register rPCONF is used as presuming the input, output or special function of the pin; Data register rPDATF [0: 8]Correspondent to the data on GPF0- GPF8 pin. Every the unit of the read-write register rPDATF is correspondent to the reading or writing of the pin. For example, CCLK rising edge sequence is to write 0 to GPF1 first, write 1 more that is got, the time delay procedure is circulated by for and realized.

Been circulating and waiting all the time

CCLK puts the data of 1 bit into DIN in each rising edge, it is low to put GPF1 first, get 1 bit data ready in GPF0, each byte on in again high to put GPF1, by circulation config_data_array ‘ ] according to ahead of low order getting more high-order order load FPGA.

FPGA configuration file of Xilinx is the same in magnitude, have nothing to do with the complexity of logic design within FPGA. Take 100,000 FPGA XC3S100Es of series Spartan_3E as examples, its configuration file fixing is 581 344 bit, if the clock cycle of CCLK is put as 2& mu; S, it is about 1.2 s to dispose time.

5 experimental results are verified

Verify the environment: The hardware adopts breadboard and Wuhan developed by oneself and creates Waite Company: JTAG hardware simulator; The developing instrument ISE8.1 and Wuhan that the software uses Xilinx Company achieves integrated development environment ADT 1000 of Waite Company (support ARM7, ARM9) .

Utilize Verilog HDL writer led. V circulating reveals 0 – F at seven nixie tubes, adopt: ISE8.1 compiles, synthesizes, shines upon, overall arrangement routing. Produce led used for programming specialized PROM. Bin file. Will use a simple C procedure. In bin file convert the intersection of ASC? and yards of file to, duplicate, reach dispose data array config_data_array the intersection of ASC? and yards of file and then ‘ ], then compile the configurator, configuration data and system program under the environment of ADT, will produce. Bin file burnt and written in Flash through JTAG mouth. After power up again, FPGA disposes normally, the experimental result and preserving compatibly.

6 conclusions

FPGA based on ARM disposes scheme structure from bunch simply, the interstar connection is easy, software programming is simple, very suitable for embedded system design. Though this controlling circuit was designed for FPGA of Xilinx Company series Spartan-3E, revised and can also be used in other serial FPGA devices a little, so have certain commonability. In addition, because FPGA has flexibility that can be disposed repeatedly, can burn to write Flash in the embedded system long-rangely through the serial port, net mouth, reconstruct the system function, it is possible that it is offered for intelligent maintaining online, function recombinating and online staging of the apparatus,etc. that this kind reconstructed technology online, and the flexibility is very strong. The scheme that this text puts forward draws lessons from meanings to digital system design, there is broad application prospect.

When not designing, carrying on the intersection of FPGA and prototype prove to ASIC, because physical structure different, code of ASIC must carry on after the certain conversion regarding input of FPGA as

In modern integrated circuit design, exactly indexes increase for scale and complexity of the chip. While especially designing the procedure in ASIC, the time to prove and debug accounts for 70% of total time limit. In order to shorten verifying cycle, on the basis of traditional artificial verification, a lot of new verification means have emerged, the verification that proved such as affirming, coverage drove, and the one that employ extensively, because of the programming device of scene (FPGA) Prototype authentication technique.

Adopt FPGA prototype technology to prove ASIC designs, needs to design ASIC to turn into FPGA and design at first. But ASIC is based on the standard cell library, FPGA is based on the look-up table, the difference on ASIC and FPGA physical structure, it is determined that ASIC code needs certain modification and could be transplanted to FPGA. Should notice this only the intersection of physical structure and different done on code conversion, not changing its function, so this kind of modification of the code can only confine to a certain limit.

Basic principle

The procedure that proves on the basis of FPGA prototype is because of the programmable characteristic of FPGA, the prototype technology based on FPGA has already been adopted extensively. Compared with simulation software, the intersection of hardware and characteristic of FPGA can let, design, run at higher frequency, accelerate emulation. On the other hand, can run side by side and design peripheral circuit and application software in ASIC chip design in earlier stage, verify cycle after shortening the chip. FPGA prototype is verified and other verification methods are different, any kind of other verification methods is a link in ASIC prove, but FPGA proves it is a series of development. Because FPGA and ASIC have nothing in common with each other on the structure, characteristic, ASIC is based on the standard cell library, what FPGA used is the great cell module that the manufacturer offered, so should carry on the register transport level (RTL) first Modification of the code. Then shine upon FPGA device, shining upon the tool will optimize logic to RTL code according to the constraint condition set up, and shine upon and produce netlists to the basic cell of the selected FPGA device. Then carry on the routing of overall arrangement, turn into information such as configuration file and sequence report. Preface can meet constraint condition, can pay download with configuration file at that time. If sequence can’t satisfied to restrain, can the intersection of preface and piece come on, confirm critical path at the report through software, optimize sequence. Through revising the constraint condition, or revise RTL code to meet the demands. Code needing changing

The memory cell of memory cell must carry on code change-over, the memory cell in ASIC is usually by customizing for Memory Compiler that the factory offers, it can produce. Gsp. Files such as v,etc.. . V file is only used for doing function emulation, usually can’t be comprehensive. When and final the sheet, only need to offer the standard to taking the place of the factory. If regard memory cell of ASIC code as the input of FPGA directly, usually the synthesizer can not come out synthetically, can come out synthetically, want, spend a long time too, and resource consume more and characteristic does not kind. And FPGA manufacturer has actually already offered the memory cell proved and optimized. So memory cell needs to carry on code change-over. In the unit digital circuit of the clock, the clock is that the whole circuit is the most important, most special signal. In ASIC, puts the clock tree with routing tool of overall arrangement, utilizes PLL offered to the factory to design the clock. Has usually already disposed certain amounts of PLL macro elements in FPGA, and there is overall clock network optimized to the clock, generally enter within FPGA through the particular overall clock base pin of FPGA, and then adapted to the overall clock network through the overall clock BUF, such a the intersection of clock and network can guarantee identical clock every the intersection of delay time and difference of flip-flop can be ignored along reach chip. So the clock unit is needed changing. Increasing the flowing water because realizes the structural difference, the unit within FPGA device delays time long-rangely when the basic gate cell of ASIC prolongs. Cause it on condition that design too, ASIC can meet its sequence, but FPGA is probably unable to be satisfied. For the need that proves, while revising ASIC code and realizing FPGA prototype, the ones that realizes to ASIC flow the water structure meets the need of hour to increase the flowing water in FPGA appropriately. For example put into the register in a very long association logical path. As shown in Fig. 1. Increase flowing water of Fig. 1 Design in fpga design synchronously, it is the important principle that should be followed to design synchronously. It is apt to cause the circuit to be in the metastable state that it is designed that asynchronous, the burr emerges. Turn it to FPGA while designing as designing from ASIC, should carry on the careful synchronism. Embody in choosing, unity resetting, synchronous sequence circuit design of the function module of main clock specifically. It can replace the door control clock to make to use the clock in FPGA design. In the design of ASIC, in order to reduce the power consumption, use the door control clock (clock gating) ,The structure of the door control clock is shown as in Fig. 2. When writing effectively, the data are written into the memorizer, while only writing it is effective, the register will be turned over, so can reduce the power consumption. 2 door control clocks of synoptic diagrams of Fig. Because of the asynchronous characteristic that is designed, to FPGA, use this kind of door control clock to produce burrs easily, lead to the fact the data are incorrect. So in FPGA design, use the circuit with enabling signal to replace the clock circuit of the gate. Can come to realize the enabling signal of the clock in the front of register in addition, MUX, as shown in Fig. 3. The present FPGA manufacturer offers and can enable directly, the register of the pin of synchronous SET and RESET, as shown in Fig. 4. Fig. 3 produces the enabling signal of the clock with MUX There is register that clocks can enable in Fig. 4 FPGA Fully utilize existing IP kernel FPGA manufacturer and third party manufacturer in FPGA to already realize and optimize kernel of a lot of typical IP, for example Xilinx has offered basic logic, a large number of IP kernels such as bus interface and I/O, video and image manipulation, digital signal processing, memory interface, microprocessor, control device. Can fully utilize these resources during code change-over, improve design performance optimally to the code. If use SRL to realize the shift register in FPGA, replace tristate bus line and ternary MUX with ternary Buffer, improve the arithmetic unit and code of the finite state machine.

Realization of code change-over

The ones that form the contract and help the microelectronic centre of the university ” The 32-bit microcomputer high performance embedded CPU is developed ” The project, in order to guarantee the reliability of the function before the sheet, customize high performance embedded CPU bc320 to the 32-bit microcomputer completely and verify the prototype.

Design FF1152 which adopts Memec Design Company to develop the board. This board has used XC2VP30 in Virtex – ? Pro series chip of Xilinx. This FPGA has 30 816 logical units, there are more than 300,000 ASCI doors in other words. Have Block RAM on slice of 2Mb, mouth of 644 I/Os besides. Having adopted full automaticity of Xilinx, intact integrated design environment ISE 7.1i, it is Synplify Pro to carry on the tool that FPGA uses synthetically.

Use ASIC RTL code of bc320 as the input of FPGA, concrete code change-over is as follows.

Has stored and used a lot of SRAM in cell design, such as SRAM in Icache. Decide which kind of unit is adopted to replace according to width of required RAM, depth and function when FPGA realizes. Xilinx has offered RAM, Block RAM and LUT RAM outside slice. ISE has offered two kinds of concrete implement methods: IP generator (Core Generator) And language template (Language Templates) . One in Xilinx fpga design design the input tool importantly with IP generator, it offers a large number of Xilinx and maturity high-efficient IP kernel which the third company designs. Here is produced and called a memorizer (Block Memory) with Core Generator Solos memory module. Core Generator offers a memorizer with graphical way to set up parameter, its interface is shown as in Fig. 5. The magnitude of a memorizer is made according to magnitude of vector, an ordinary unit vector only costs 4 times 512

1. Foreword

Under the promoting of Moore law, semi-conductive trade technology develops very fast, the integrated circuit transistor quantity is turned over time per biennium, require higher and higher to the data rate of Communication link between the devices or systems. And the decrease with nodal craft has promoted the Moore law. Reducing the volume can hold more functions in unit logic, improve working speed, logic density and integrated level, reduced at the same time. Usually raise the data rate by advanced design method and technology, support fixed net and wireless communication, computer, storing, military application and radio electronic system to send and receive the mass data, in order to meet data transmission and bandwidth requirement increasing constantly.

Front products such as microprocessor and FPGA,etc. have adopted 65 – nm technology. The subsequent types of these products will adopt 45 put out this year – nm or 40 – nm craft. Smaller craft size means the channel length of the transistor-resistor logic is reduced, the connection between logic gate is shortened, cause more quick switching time and shorter transmission delay each other. The craft node is reduced favorable to logic work, optimize to the efficiency, realize high density, high speed data transmission.

Today, Communication and I/O (I/O) The data rate of most advanced transceivers is in 5& ndash in the standard; In 6 Gbps range. For example, there is CEI/OIF 6G, 2X XAUI (6.25 Gbps) of network Communication in numerous standards ,Computer I/O total collinear PCIe 2.0 (5 Gbps) ,Store SATA III/SAS II of the area network (6 Gbps) When.

® Stratix® IV GX FPGA is based on 40 – nm technology. Its logic framework of kernel has logical unit 570K (LE) ,Support to realize large-scale SOC (chip system) fpga design and application. The high-speed transceiver has adopted the topological structure all sides, 48 passways at most, the data rate is up to 8.5 G Gbps. In a word, Stratix IV GX FPGA of Altera has the most high density, preferably characteristic and the lowest power consumption. Utilize the advantage of 40 – nm, rely on mature transceiver and memorizer interfacing, Stratix IV GX FPGA system bandwidth is unprecedented, have an excellent one. Stratix IV GX FPGA and HardCopy® IV Advantage that ASIC has combined and realized FPGA and ASIC seamless prototype and developed.

This text introduces the characteristic of Stratix IV GX FPGA, capacity and goal application in detail technically. ” 2. Development trend and demand of the high-speed periodic line ” Have contained the technology, market and demand for employing trend and high-speed transceiver, including the new I/O interface standard at a high speed (PCI Express Generation 2 (PCIe 2.0) , Hyper Transport 3.0 (HT 3.0) , the interface of Interlaken, public radio frequency (CPRI) And frame interface Level 5 (SFI-5) of SERDES ). ” 3. 40 – nm craft node and transceiver ” Introduced capacity and characteristic of Stratix IV GX FPGA, how and it met even surmounted technology and standard requirement. ” 4. The architecture ” Involve important and unique capacity, technical superiority and performance criterion, including high-speed periodic lines and transceiver craft nodes, and the architecture,etc.. ” 5. The clock recovery of the composite signal ” Discuss the clock recovery circuit (CRC) . ” 6. Carry to the end balancedly ” Introduce the projector and balanced function of receiver. ” 7. Advanced clock and time sequence happen ” Introduce the Shakers of different types. ” 8. The power consumption and shaking ” The built-in self-test of the discussion shakes(BIST) , the noise, signal completeness and bit error rate (BER) , the circuit takes place in power consumption management and power completeness, rigorous sequence, and the high-speed standard is supported etc.. ” 9. The conclusion ” Summarize this text.

I came up with this problem when I was doing my project. There are more than 66 parallel pinouts on the Spatial Light Modulator (SLM) chip to be controlled. I generated the commands on the computer and then send them to the fpga via DMA FIFO. It worked fine when there were only 64 lines. I can transfer a 1D U64 array to the target and then split each U64 data to 64 booleans.
See also the example ‘DMA buffered acquisition’ in LabVIEW 2009.

When there are 66 bits, I just created 2 FIFOs for the first place, one of which was type U64 while another is U8. I found it very hard to synchronize the 2 FIFOs. Some memory (I can’t remember exactly where it came from) recalled me using case structure to decimate the 1D array. So I interleaved the data to a 1D U32 (because there are 32 bits on Bus A and Bus B) array, and decimated them on the fpga side. By doing this I *wasted* 32×3-66=30 bits per command, which is tolerable and flexible.
Host vi:

Target vi:

We set up the order of procceding by creating a type defined enum (Enum ‘Bus B’ in the figure) and telling the state machine which state the next should be. Note that we need to create a for loop in each iteration. Because we want to dequeue the buffer several times to achieve the commands for all lines.

0 foreword

With the development of FPGA and large scale integrated circuit, there are new methods in the realization of data interchange. In this design, FPGA finishes the serial port intelligence signal (TXD, RXD) Exchange,to last line (RTS, CTS, DTR, DSR, DCD, RI) time slot interchange chip Exchange. Inside has hardware conflicts that monitors the function, can detect automatically 2 terminal stations are connected to the same signal channel or 2 signal channels and connected to the same terminal station at the same time, and remove the old connected state automatically and set up new periodic line. Make the original connection terminal and enter the free status in this way, guarantee terminal and signal channel time axile weldless switch. Through judging the state of RI, it can also monitor the state of the signal channel DCE, judges whether there is request in the signal channel, and report and is controlled.

The technical indicator is as follows: Exchange the scale: 40× 40× 8; Maximum switches over build-up time: 200μ s; The line maximum of shaking hands transmits and delays time: 125μ s; The data link maximum transmits and delays time: Smaller than 1& mu; s; Serial data rate: 8.192 Mbps.

A hardware implementation

Data switching matrix under accusing of control of unit, exchange physics terminal data port with data port of signal channel. 40 switching matrixes including DTE ports (include interface of 24 DTEs, configurated interface of 16 DTE/ DCEs) ,40 DCE ports (include interface of 24 DCEs, configurated interface of 16 DTE/ DCEs) . The switching matrix of the data is by data link switching matrixes (TXD, RXD) , the line switching matrix of shaking hands (RTS, CTS, DTR, DSR, DCD, RI) And exchange the control module (one-chip computer realizes) Composition. Exchange control module, manage data link and shake hands line, go on and operate to 2 pieces of module continuously. The data link is exchanged and finished by programmable logic device, shake hands the line exchanges and is finished by time slot interchange device.

The switching module of data link is realized by FPGA, choose 300,000 doors of programmable logic devices to realize, its resource has already met circuit switching of data’s demands, and all right reenlargement. The line switching module chooses TSI (TIME SLOT INTERCHANGE) to shake hands Chip MT90820, has 16 to receiving and dispatching the data flow, maximum can realize 2 048& times; 2 048 passways of non-blocking switch. The control unit of the switching matrix chooses 8051 general serial one-chip computers. CPLD_1, CPLD_2 and CPLD_3 choose MAX7064, can connect 4 groups of serial ports and shake hands in the line (the functions of CPLD_1, CPLD_2 and CPLD_3 can be realized with FPGA of a bigger resource, select to finish with small CPLD here) . The function is shown as in Fig. 1.

The functions within FPGA and CPLD were all realized through the hardware description language VHDL. Function of switching over the order, reading DCE channel condition etc. that FPGA finishes the exchange, transmission of the intelligence signal. 8 bus interfaces of one Intel of its simulation (connect the control unit) ; 16 bus interfaces of one Motorola (connect the time slot interchange chip) ,Thus carry on the sequential variety of interface. All registers that the thread exchanges in the chip are identical that the data interchange state register in FPGA corresponds to looks and shakes hands, to guarantee the data link with shaking hands the line exchanges and moves ahead simultaneously. Collinear bunch and such functions as changing, framing, DTE/ DCE choose that CPLD finishes 4 groups of serial ports and shakes hands.

CPLD_1 can only connect DTE, each 6 string of DTE shake hands line (2 take place 4 charge) Correspond to 2 8 bit registers, a transmitter register, a receive register. RST/ DTR corresponds to the top 2 of the transmitter register, CTS\ DSR\ DCD\ JI corresponds to the top 4 of the receive register. (8 kHz) when there are locking signals Syning ,Each transmitter register serial shift output data, the transmission data cyclically of every other frame of 4 transmitter registers, it is 128 time slots, 128& times to make up a every frame; 8, 8.192 Mb/ s data flow (STi) ,Line switching matrix of sending and shaking hands. DTE0 to DTE3 has taken up the 0th to the third time slot in the data frame sequentially, it is all idle to remain. It is opposite to receive the course of data flow. The line switching matrix sends the data flow (STo) of the fixed frame format up to shake hands Enter CPLD, draw the first 4 of the 0th to the third time slot through the locking signal Syn, puts into corresponding receive register, and then reach the hand-shake line signal (CTS\ DSR\ DCD\ RI) of every DTE correspondingly sequentially . This is a signal channel (DCE) The Handshaking signal that the port is sent to, thus has realized and exchanged. The time slot that each DTE takes up is stationary, one DTE takes up a time slot in every frame. If DTE0 takes up the 0th time slot, so as to analogize. As shown in Fig. 2.

CPLD_2 can only connect DCE, each 6 string of DCE shake hands line (4 take place 2 charge) Also correspond to 2 8 bit registers. CTS\ DSR\ DCD\ RI corresponds to the top 4 of the transmitter register, RST/ DTR corresponds to the top 2 of the receive register. (8 kHz) when there are locking signals Syning ,Each transmitter register serial shift output data, the transmission data cyclically of every other frame of 4 transmitter registers, make up a data flow (STi) ,Line switching matrix of sending and shaking hands. DCE0 to DCE3 has taken up the 0th to the third time slot in the data frame sequentially, it is all idle to remain. It is opposite to receive the course of data flow. The line switching matrix sends the data flow (STo) of the fixed frame format up to shake hands Enter CPLD, draw the first 4 of the 0th to the third time slot through the locking signal Syn, puts into corresponding receive register, and then reach the hand-shake line signal (RTS\ DTR) of every DCE correspondingly sequentially . This is terminal (DTE) The Handshaking signal that the port is sent to, thus has realized and exchanged. The time slot that each DCE takes up is stationary, one DCE takes up a time slot in every frame. If DCE0 takes up the 0th time slot, so as to analogize. As shown in Fig. 3.

CPLD_3 is CPLD_1 and CPLD_2 amalgamation of function. According to the needs of user, under the control of FPGA, and shakes hands within CPLD through the data link, collinear crossbar transition can vary DTE into DCE, methods are similar to the collinear method of crossing of the general RS232 data to cross. Do it in this way mainly in order to regard DTE as DCE. When this DTE port is exchanged with other DTE ports, should change it into DCE port to use; When this DTE port is exchanged with DCE port, do not pay changing and still use as DTE port. After confirmed to be DTE or DCE, can be according to the methods of CPLD_1 and CPLD_2, the line switching matrix of making a gift of and shaking hands.

2 software implementation

Software implementation adopts language C to carry on the modular design, main including main program element, switching unit, inquire unit, interrupt location, have the intersection of declaration form and yuan and watchdog voluntarily. The main program includes the judgement choices of initialized disposition and every function module of the switching matrix of the data. Switch over the intersection of cell control and FPGA with the intersection of time slot and chip, carry on each carry oral switch connect, remove, connect and collision detecting and Forced Release connect. The interrupt location is and the interface which controls communication, are responsible for receiving and controlling the order coming; Information reported voluntarily in sending. Inquire that can inquire about the state of each signal channel in unit, is the signal channel asked (inquire whether the bell signal RI of signal channel is effective) . It means that destroy the plane to appear in the newspaper, appear in the newspaper regularly, to instruct the switching matrix of the data whether to operate normally or not to get on declaration form yuan voluntarily.

3 conclusions

Through designing above, can make into a single module. DTE interface can answer data terminals such as the digital telephone, digital facsimile,etc.; DCE interface can connect data channels such as GSM,etc.; DTE/ DCE interface can be disposed according to users’ demand, for example the Communication of multiple serial interface, DTE or DCE used for expanding in computer. It is good that this technology has platform commonability of the hardware, such advantages as easy that the application area is wide and the function is expanded.

FPGAs are wonderful things – but you know that; otherwise you wouldn’t be reading this. This year it will be 25 years since Xilinx shipped its first product, the XC2064, creating the name Field Programmable Gate Array to distinguish the device from other programmable logic and to rank it alongside the gate array in use for building ASICs. By 1990, there were around 20 companies attempting to play in this market, but already Xilinx and Altera were pulling ahead, with Lattice, Actel, Atmel, and QuickLogic snapping at their heels. Today, twenty years later, Xilinx and Altera between them dominate the market, QuickLogic is in the programmable devices field but distances itself from the FPGA arena, and Atmel appears to be using FPGA fabric only with its AVR processor family. Actel and Lattice have a fraction of the market of Altera and Xilinx (although dominating some niche markets, like Actel in Rad-Hard). Oh, and there are some start-ups, such as Silicon Blue, Achronix, and Tabula hovering in the wings.....

Need, finish the intersection of multiple channel and fault detection and the intersection of multiple channel and command control often in the industrial control ‘ It is very general that this kind of mulitasking is set up) ,The single CPU chip because its external control interface is limited in quantity and it is difficult to finish supervising the task directly, so it is a spanking choice to utilize ARM chip to expand and supervise the passway in conjunction with FPGA. Recommend using Atmel Company ARM7 processor ( AT91FR40162) here And the low-cost FPGA chip ( cyclone2) of ALTERA Company Use an implement method to finish the multiple channel and supervise the task in conjunction.

Brief introduction of every part of functions

Fig. 1 is a structural connection block diagram of this system. As shown, and read and write the control line to link through the data bus, address bus between ARM chip and FPGA chip, but communicate with the terminal station PC through the serial port; FPGA and the goal apparatus, through ordering the control bus to connect with bus line of fault detection.

Pursue the structured flowchart of zero-one system

A fault detection and ordering the control box

Fault detection: Sense channel trouble ( Normal) Signal Israel high ‘ It is low) The intersection of level and mode indication, it keep level constant until trouble removal if it is produced that out of order. To specific character this, adopt timer interrupt circulate, inquire way come, judge the intersection of trouble and state of passway in the intersection of ARM and the intersection of control device and end. Regular interrupt program and the order is locked the level value of the sense channel through interpret in FPGA to the intersection of ARM and address bus, then pass ARM back to judge by the data bus and send the judged result to the remote terminal finally. Adopt the host computer to inquire the way is without adopting the interrupt mode of the trouble for two reasons: On one hand usually the intersection of control chip and external limited interrupt source ‘ The majority is 4 external interrupt sources) ,It is obviously difficult for multiple target to cut off signal detection; On the other hand, produced the random reversal of level because the sense channel or Apparatus receives interfering with in short-term, cause malfunction interrupt to touch off, but be unable to cancel the fault signal when the level of the passway return to normal after stopping touching off, so it is false to form and call the police.

Command control: ARM chip judge the intersection of top management and control command that end sends first, then send the command mode to the control duct locking through FPGA address decipher through address bus and data bus.

The intersection of 2 ARM and chip and find control terminal communicate have order and the intersection of trouble and receiving and dispatching of status signal only while being long-range, so utilize a bunch of cause for gossip of ARM now and Communication of long-range PC, Communication standard is elected as RS232 standard. However, should change TTL level into RS232 level standard through MAX232 chip first on ARM chip, exceed the whole duplex Communication of 15m as to distance, send, receive both ends respectively and one RS232 transfer the intersection of RS422 and conversion module of level to, in order to increase the Communication distance.

The function module explains within 3 FPGA

Detection and controlling circuit structural relationship are shown as in Fig. 2 within FPGA.

Logic structure within Fig. 2 FPGA

ADDR2- 0 address lines of ARM chip enter the Decoder decode1 to produce No. 8 to export after carrying on the address decipher with enabling signal of chip selection (can set up one peak output for route of the intersection of decipher and modules inside the FPGA, can expand multiple channel to in real application) ,Low No. 4 is used for in the sending channel of order, it is high No. 4 is used in the sense channel of trouble, it can enable the data bus of signal control to read and write.

When ARM chip receives the coded command of sending a message, and give the corresponding address (the passway is numbered) in the serial port receives the interrupt service subroutine immediately With the data ‘ Command mode) In FPGA. The actual output of the Decoder, as latching the clock of D flip-flop of corresponding passway, but as selecting finishing controlling correspondingly in output of the passway after the state of the data is locked by the flip-flop.

ARM chip inquire to all sense channels in turn after timer interrupt produces and enters the service program, while inquiring to that there is trouble of passways, the fault signal combines and chooses the signal of thorough fare to be sent to through nand operation the data port and read.

Pay attention to the question in fpga programming

A delayed disposition

While carrying on command transmission and fault detection through address bus and data bus, FPGA uses as ARM ordinary peripheral hardware of chip. And ARM chip sets up the speed visited to the outside and should be well below one slice of internal memories, so will set up the correct wait cycle visiting in ARM. The time delay cycle when offers in ARM is 0- 7, can find the appropriate wait cycle of peripheral hardware through debugging, this systematic waiting for cycle to set up as 5 according to actual test, see ARM procedure explain by concrete configurate method.

2 connections of reading and writing the enabling signal

Can find out, write the enabling signal NWE and read the enabling signal NRD and should be regarded as the data link (DATA0- 5) from Fig. 2 Three-state control signal connection,even when ARM chip does not have other peripheral hardware can’t default. Because the power up of ARM loads program time and should be longer than the same system the procedure of FPGA dispose time, and detection and control duct of FPGA link with data bus of ARM chip, FPGA load data bus will have corresponding logic level value of passway finish, ‘ It is not the tristate) ,It last ARM this chip for on-chip Flash chip at not cooking and lasting proceduring or power up loader and FPGA conflict( The data are locked by logic) ,Cause and can’t position the operand and make and read and write failing correctly.

1 2

Embedded processor cores for DSP, microcontroller and microprocessor functions are becoming increasingly common in FPGAs. Both Xilinx and Altera have long offered their own embedded soft IP cores, and a growing trend is to also support the integration of third-party hard IP cores, such as the PowerPC or ARM families. Gartner estimates that approximately 40% of all FPGA designs include embedded processors.  The combination of a flexible FPGA platform and a proven, high-performance core saves designers time and effort. And the FPGA suppliers are making it even more efficient through offerings such as Xilinx’ Extensible Processing Platform for the ARM Cortex-A9, which makes customizing the FPGA device for specific function or design requirements easier.

But with the addition of larger and more complex embedded processors, combined with the complexity of the overall leading-edge FPGA architectures, designers are faced with unprecedented verification challenges. A ‘fully loaded’ FPGA with multiple embedded cores and millions of logic cells can literally bring a traditional simulation approach to its knees. Just the density of these devices alone is daunting. But consider that there is also a need to execute and verify software along with the hardware, and designers are looking at multi-million cycle simulation challenges.

GateRocket’s Device Native approach addresses head on the simulation challenges of designing FPGA with embedded cores.  With a Device Native approach, which is enabled by our RocketDrive tool, the design team can connect the actual processor in the target FPGA into a simulation environment, significantly accelerating the verification process. The processor in the FPGA can operate in the simulator environment. Meanwhile the design team can focus on behavioral tests of the circuit blocks designed by the team and those purchased as third-party IP.  The design team can move forward without a major simulation bottleneck. 

While simulation performance is a major challenge in these large, embedded-core-based FPGAs, the RocketDrive offer more than just verification throughput benefits. With it, designers can simulate their designs with silicon-level accuracy and identify problems that typically go undetected until system-level debugging in the lab.  In this way they can also spot problems early in the design cycle when they are much easier to find and fix.

We’ll be talking about how this Device Native approach can help designers using embedded processors at next month’s Embedded System Conference in Boston. On Wednesday, September 22 we’ll be leading a technical session beginning at 3:15PM in Room 103 that examines the challenges of debugging and verifying complex FPGAs. The session will provide an in-depth overview of our solution, featuring the RocketDrive and RocketVision verification and debug tools that have proven to significantly reduce the time and effort involved in bringing up working FPGAs, whether for use in production systems or as ASIC prototyping platforms.

The global FPGA whole market expands rapidly in recent years, among them Design Win quantity correlated to embedded FPGA processor is being increased rapidly, potentiality is enormous. Just like the box which opens Pan Dora, have the processor kernel of the operating system or real-time operating system of can run ing, it is believed that FPGA is entering in the real meaning on a large scale embeddedly and designing the field.

From Xilinx, Altera to Actel, Lattice, FPGA offers the commercial city there is ” hard ” that can be realized by FPGA logical module The kernel, or ” soft ” that can run in FPGA structure directly Kernel processor. The hard nuclear advantage can offer more quick data-handling capacity, the so-called soft core needs PLD software that FPGA manufacturer offers to carry on the disposition, then solidify in FPGA. Compared with hardcore, the soft core has better flexibility, can carry on the arbitrary disposition in the goal device, choose IP module and peripheral hardware according to designing the need to be flexible specifically. Xilinx also supports MicroBlaze two soft kernels of 8′s PicoBlaze and 32-bit microcomputer besides hardcore of embedded PowerPC of the 32-bit microcomputer. Mr. Liang XiaoMing, manager of Xilinx advanced product market of the Asian-Pacific area, represents, high side and low-end FPGA embedded market are mushroom, so Xilinx will give consideration to and develop these three kinds of embedded processors continuously. Altera only offers the soft core, MicroBlaze of its 32-bit microcomputer Nios II soft core processor and Xilinx is well matched, all the most general embedded FPGA processor on the market at present too. Nios II and MicroBlaze have all increased the support of the dot element floats to new IEEE754 compatibly recently. The products of Altera company the Asian-Pacific area and channel engineer Mr. Wang DongGang of marketing explain, IEEE754 standard defined that represents a set of forms of the floating point in the computer. This characteristic advantage lies in expressing figures more accurately, so long as need high-accuracy assumed occasion to consider improving calculating precision with the processing unit of floating point. Just the same as the floating point representation becomes the standard in Pentium series CPU of Intel, increasingly many embedded application needs this characteristic, for example the process is controlled, image manipulation, motor speed shows etc. accurately in the car. Another FPGA supplier Actel expects to compete with Altera and Xilinx on the aspect of different markets. Actel has imbedded ARM7 microprocessor kernel CoreMP7 of the 32-bit microcomputer in its FPGA. Traditional embedded processor, such as ARM and MIPS, its processor IP is very difficult to be protected in the design procedure based on soft core, so ARM or MIPS kernel can’t be offered to FPGA manufacturer in the form of soft IP all the time, but is different from FPGA based on SRAM of the mainstream, Actel can guarantee the safe operation in the device of commercial IP on the basis of Flash technical FPGA. The manager Mike Thompson of Actel Company IP market represents, compared with the summation that uses in all other similar processors, the proportion that ARM processor is adopted in the design is 5 – 1. CoreMP7 and ARM7TDMI-S are fully compatible, most customers used ARM processor kernel in the past. Have ready-made ARM codes, and developing instruments familiar withed furtherly. Can save Actel customer’s development time to the familiarity of ARM framework. Choose different structural products with Actel then fight in different parts other markets to be different, Lattice hopes to launch competing with Altera and Xilinx directly, seek the difference while expanding the products constantly. In embedded processor, Lattice is extending such competitive tactics too, like MicroBlaze and Nios II, LatticeMico32 soft core processor of Lattice is very apt to imbed in FPGA too, the gentleman emphasize that Lattice IP and employs and designs the manager to thank and ship on a long voyage, the one different from the former two is, Lattice has opened HDL source code of LatticeMico32 and peripheral component, users can understand microprocessor nuclear structure and internal detail of the work better, can revise codes by oneself at the same time, increase the transplantation that is designed. The developing instrument of the software, including compiler, collecting device, interface unit and debugging device based on GNU open the source code. Even LatticeMico32 soft core processor can be used in the products Lattice Company, including in FPGA of ASIC, structuring ASIC and other manufacturers. Most embedded systems only take a kernel, such as consumption products, network Communication and industry’s system. The situation used for advanced data processing often of the multi-processor, for example the more complicated algorithm or having application of a large number of complicated protocol processings to some video processing, may need two or more embedded processors. Can realize a plurality of processors in one FPGA, for example two MicroBlazes or Nios II, or most mesh. Not formulary in this, totally depend on customer’s desired goal comes flexibly that realizes different application modes, until one MicroBlaze, as main control unit, another one make the special task processor; Or two MicroBlaze mutual independent execution their own tasks. Just because of this, it is incomparable that this advantage has generally already solidified the peripheral hardware and customized ASSP and ASIC of the function. For this reason, have already arisen at the historic moment too to the applied debugging tool of polykaryon, Altera and Xilinx have all obtained support of the supplier Lauterbach of the German famous microprocessor developing instrument, TRACE32 ICD-Debugger and TRACE32 PowerTools debugging tool of Lauterbach supports multinuclear PowerPC, development of MicroBlaze and Nios II system. The main restriction of the processor of the soft core lies in the characteristic of the processor, but the characteristic of the embedded processor is not a very great problem in FPGA, in that key function, such as various complicated DSP algorithms, can realize with higher speed through the hardware, there are a large number of hardwire multipliers or ride the totalizing unit in a lot of FPGA nowadays, can use the accelerator of the custom hardware. For needing to improve the software engineer of embedded software performance, the accelerator of the hardware is a very important tool, compared with code running in the soft core, running speed of FPGA accelerated code can be nearly several pieces of order of magnitude, the spent power is reduced greatly. The design of the accelerator of the hardware is FPGA hardware design category to challenge lying in, need developers to be skilled and grasp HDL, logic synthesis and complicated sequence are designed, spend a large amount of time at the same time, so the design of the accelerator of the hardware becomes the bottleneck. Altera developed C2H (accelerate from language C to hardware) recently Compiler, can automatic generation hardware accelerator,key one, especially last hardware accelerator and not run on FPGA at C codes including complicated mathematics logical algorithm, to put it briefly, the work that C2H compiler needs doing is: *Analyze the intersection of software and code, confirm, appear characteristic bottle cervical * function in Nios II IDE highlighted to reveal the required function, the right key clicks and accelerates * to look over Nios II C2H compiler result, revise C code depending upon need, it is ESL tool to optimize C2H compiler, to the definition of ESL tool according to Synopsys, ESL tool offered conversion to the hardware description language of language C. ESL has two pieces of master design procedure: High level language synthesize system modelling, high level language including module turn into and hardware accelerate synthesize, the method that the module turns into can aggregate C code into RTL code directly, realize DSP module in FPGA directly, this kind of method can raise design efficiency to a great extent, but need to have thorough understanding on C synthesis tool; If choose the embedded processor, can utilize FPGA resources to establish a hardware accelerator for it, this way just puts key operation in FPGA logic to carry out in the form of accelerator of the hardware, it is simpler to compare the way to produce DSP module, C2H compiler is that the hardware accelerates tools. The system modelling means that writes the simulation model, thus the artificial speed of the boost system with C ++. Altera and Xilinx all launch the relevant ESL plan recently, develops the design tool cooperatively with the master ESL manufacturer, the support to embedded processor kernel of these tools includes among them too. By using ESL tool, the software or system engineer not good at FPGA hardware design in the past can enter FPGA field, the quantity of embedded design correlated to FPGA will still further increase.

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The video monitor system is the important assembly of railway station, airport, bank, place of entertainment, shopping center even family security personnel. Until safe risk increase, monitor and record demand of incident with use the mode to increase sharply while being many kinds of to vision. So, the new architecture must offer the expansibility for spanning the cost-effective scheme that the miscellaneous video monitor system requires day by day of a whole set of. Pressure, new CODEC standard, extensive requirement (including advanced target detection, sports are surveyed, target tracking and goal tracking performance) day by day of listing time ,These are just that new videos control several items of the challenge that the framework faces. It is to expanding to the demand of realization of different performance ranges following challenging.

As to from low-end to high side and any video monitor system from single machine to PC Expansion cards, Xilinx FPGA is all ideal solutions.

The video controls and DVR system

Digital video video recorder (DVR) in the digital monitor system Adopting advanced digital video compression rapidly. Most DVR manufacturers are from MPEG4 to H.264 high sharpness (HD) CODEC shifts, and compress the demand for the speed to thereupon increase to the definition. Special purpose chip (ASSP) Very useful to employing in enormous quantities, but lack flexibility, the development cost is high, and development time is longer; Most advanced digital the intersection of media and processor can only carry out H.264 HD decode . The best solution of meeting H.264 HD performance requirement is to use one FPGA to add a outside DSP or digital media processor.

Use low-cost Xilinx FPGA, can go still one step further, offer sport survey, the intersection of video and zoom, the intersection of color and spatial switching, the intersection of hard disk and interface and the intersection of DDR2 and memory interface, can also reach two times 27 – MHz ITU-R BT656 data flow time division multiplex transmission in a 54MHz data flow, offer the video for DSP processor to accelerate at the same time. Want, get one ITU-R BT656 in the data flow two the intersection of ITU-R BT656 and the intersection of data flow and multiplex transmission, only need a passway video port to transmit intact two passways of video datas independently. Offer the interface for oral digital media processor of input end of only one ITU-R BT656 video, this kind of implement method is very useful. It is a block diagram of such a suggestion framework that Fig. 1 shows.

For using the instrument company DaVinci processor of Dezhou (only have a ITU-R BT656 video input port) DVR design,last a have two pieces or ITU-R BT656 data flow time division multiplex transmissions more got by one of VLYNQs in data flow, then could deliver it to DaVinci processor. Using the above-mentioned implement method, you can transmit the video flowing with much less I/O pins, and can reduce the system cost, because the capsulation of the device can become smaller. Fig. 2 shows for this block diagram designed.

PC Expansion cards DVR system

Over the last ten years, the PCI bus offered very good services to PC. However, the current required bandwidth of PC Expansion cards DVR system, has already gone beyond the intensity of the PCI bus in power greatly. Video data not compressed (after removing the blank frame) About 165Mbps. Like this, in a situation that the overall PCI bandwidth is 1Gbps, you can only use 6 pieces of not video gathering or video reproducing device through compressing with on a PCI bus at most. You can narrow the bandwidth on the bus line on the Expansion cards with MPEG4 CODEC chip set, but this will increase the cost, and make you limited by existing MPEG4 chip set.

PCI Express(PCIe) Technology makes the flowrate promote greatly. PCI Express resolves into a plurality of passways. At it is at each piece in passways every direction include one of differentiatings correctly,direction each differentiating to data flowrate is for 2Gbps. Each PCIe slot on the mother board has one’s own passways, these passways do not share with any other slots. The configuring to 16 passways (also call x16) of every slot , 8 passways of (x8) , 4 passways of (x4) Or a passway (x1) . PCIe allows per calorie of data bulk 32Gbps from 2Gbps of x1 passway to x16 passway offered to vary. There is the flowrate of PCIe data, you can get rid of each PCI card and 6 not restrictions of the compressed video passway.

Use and same design shown of Fig. 1, can be through replacing the digital media processor and be buffered the method to PC of the video flowing by PCIe bus line with PC, realize PC Expansion cards DVR system relaxedly and rapidly. The analog-digital converter of the video produces four independent figures ITU-R BT656 and flows, then these flow and is sent into low-cost Spartan? -3 devices carry on the preconditioning. In FPGA, the video data removes the blank frame and moves ahead simultaneously, bale PCIe appropriately, then feed to Xilinx PCIe kernel. Then software can read and broadcast video that input into, to process its, or store it to the magnetic disc. Fig. 3 shows and controls system design for PC Expansion cards video.

Xilinx video and image manipulation algorithm

From heterogeneous video converter, two-dimentional FIR electric-wave filter and simple result to covering and alpha blending,etc. of the on-screen display, and then reach form and color spatial switching, Xilinx FPGA is all real-time digital video, image manipulation and ideal platform filtered. Table 1 has listed the application guides of some daily videos module group IP.

Xilinx FPGA unparalleled DSP handling capacity means supporting very high definition (image quality is up to 1080p) ,And can narrow the size of the large-scale DSP array. Xilinx FPGA is a hardware that can be programmed again, have, it, you can try novelty, high performance, video and picture algorithm based on hardware easily, achieve and pole the result which sees the shadow, make your end product out of the common.

Ready-made IP

Xilinx has offered the video module group IP, for fast design, emulation video monitor system, realize and verify video and image manipulation algorithm. China includes basic primitive and advanced algorithm for designing DVR.

In addition, Xilinx and cooperative partner have offered a series of compressed encoding, decodes and compiled code solution, from offering the ready-made kernel to person needing realizing fast, until offer structure reference design of module and hardware platform to the person that hopes to make one’s own products out of the common through high quality and low bit rate.

Use Xilinx FPGA for the extremely strenuous treatment task in some compiled code module, mean you can support the multiple channel HD code, save valuable systematic processor cycle, through reduce or get rid of the intersection of DSP and the intersection of processor and array, save cost in a large amount, and from interface to further video processing multi-function and ability integrate in the systems easily. The most important thing is, FPGA has offered the extensible solution, thus can support different disposition, extra passway or new compiled code scheme in the identical system.

Xilinx FPGA can realize the new peripheral hardware further reduces DVR system cost through the systematic logic sum of ruggedization. Xilinx and cooperative partner also offer the system interface for fast development of the video monitor system: VLYNQ and EMIF interface of advanced memory interface, PCI Express, Dezhou instrument, interface of hard disk interface and ITU-R BT656.

Xilinx tool simplified and designed

Xilinx System Generator for DSP allows to use Xilinx video module group IP to construct and debug the high-performance DVR system in Simulink. Use System Generator to develop the video processing algorithm of concurrent implementation, can get the design that is prove and can be carried out easily completely.

Xilinx has already developed the new videos module group IP of various process pretests. You can construct the video / image system easily by towing and showing the module in System Generator, thus save and write these valuable time to basically construct the module with HDL language.

In order to deal with the bulky video data flow of developing from board to PC, System Generator for DSP has been introduced into another kind of novel high-speed hardware in coordination with emulation (pass interface of Ethernet) . This kind of interface allows low delayed high flow capacity, the fact proves it is extremely useful to constructing the video / image system in System Generator environment.

Another kind of design tool based on MATLAB language is AccelDSP synthesis tools that Xilinx developed, this is a tool based on advanced MATLAB language, it is that Xilinx FPGA designs DSP module that used in. Tool this can realize the intersection of floating point and automatic change-over to get fixed point, can produce very synthetic VHDL or Verilog language, and can be in order to prove that establish the test platform. You can also produce fixed point C ++ models or System Generator module with MATLAB algorithm. Is AccelDSP Xilinx XtremeDSP? A key assembly of the solution, it collects the most advanced FPGA, design tool, intellectual property right kernel, partnership relation, design and education and serves an organic whole.

Conclusion

In the video monitor system, the video signal is produced by a plurality of cameras. FPGA receives the digital video of ITU-R BT656 form from the video decoder, then reveal the video output that is dealt with to the monitor, output it to the digital media processor or DSP to store in the hard disk after compressing at the same time.

Utilize Xilinx FPGA, you can make according with canonial systemming, different from producting of rival one’s own, still obtain the best equilibrium for your application at the same time. Utilizing the video module group IP of Xilinx, you can construct DVR system with high flexibility and expansibility easily, thus satisfy the market of low-end as well as satisfy the advanced market. Through integrating PCIe kernel and video module group IP together, you can develop low-cost PC Expansion cards video monitor system. Use VLYNQ kernel in Xilinx FPGA, you can connect the numerous video flowing from multiplex camera to DaVinci processor of TI easily through Xilinx FPGA.

Integrating algorithm synthesis, system engineer and hardware artificer based on MATLAB favoring the algorithm developer of AccelChip and Xilinx System Generator The graphic design procedure used is combined together. It uses abundant MATLAB language and tool box attached to establish complicated DSP algorithmic System Generator IP module. Use these tools through amalgamating, can utilize this most valid means of hardware modeling for realizing while designing the group, thus let the algorithm developer totally participate in the design process of FPGA, and finish the more high-quality design more quickly.

Today Insiderslab.com issues new research reports on large insider trades found in the above Blue Chips or Penny Stock companies. Insiders refer to company C-Level Officers (CEOs, CFOs, COOs) and Directors who are involved in making critical corporate decisions. There are thousands of insider filings on the stock markets every day. Insiderslab.com strives to turn this massive raw data into usable information that investors can use to do better research for their investments. 

Today, Insiderslab.com releases the following insider trade reports:
(Read full report by clicking the links, you may need to copy and paste the full link to your browser.)

Altera Corp.: Open-market Sale made by company C-Level Officers on Aug 3rd, at trade price (US$27.61 – 27.77). Disclose date: Aug 4th.
Read Full Report: http://www.insiderslab.com/PR/081310A/ALTR/Altera (NASDAQ: ALTR)

Netflix, Inc.: Market Option Sale made by company C-Level Officers on Aug 10th, at trade price (US$123.64 – 125.00). Disclose date: Aug 12th.
Read Full Report: http://www.insiderslab.com/PR/081310A/NFLX/Netflix (NASDAQ: NFLX)

Texas Instruments Inc.: Open-market Sale made by company C-Level Officers on Jul 30th, at trade price (US$24.66 – 24.67). Disclose date: Aug 2nd.
Read Full Report: http://www.insiderslab.com/PR/081310A/TXN/Texas-Instruments (NYSE: TXN)

Brocade Communications Systems, Inc.: Open-market Sale made by company C-Level Officers in past 90-days.
Read Full Report: http://www.insiderslab.com/PR/081310A/BRCD/Brocade (NASDAQ: BRCD)

JDS Uniphase Corp.: Open-market Sale made by company Directors on Aug 2nd, at trade price (US$11.01). Disclose date: Aug 4th.
Read Full Report: http://www.insiderslab.com/PR/081310A/JDSU/JDS-Uniphase (NASDAQ: JDSU)

Expedia Inc.: Market Option Sale made by company C-Level Officers on Aug 4th, at trade price (US$24.00). Disclose date: Aug 4th.
Read Full Report: http://www.insiderslab.com/PR/081310A/EXPE/Expedia (NASDAQ: EXPE)

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Every day, Insiderslab.com research analysts spend hours to track and monitor insider trading activities in the U.S. markets and issue Insider Trading Research Reports every day. Watch the next report tomorrow for one of the following research highlights:
1. Down by Half Purchases made by C-Level officers, Directors, and 10% shareholders
2. Large purchases/sales made by C-Level officers
3. Large insiders sales at 52-week highs
4. Large insider purchases at 52-week lows
5. Consensus purchase/sales by a group of insiders

About Insiderslab.com:
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Insiderslab.com is not a registered investment advisor and nothing contained in any materials should be construed as a recommendation to buy or sell any securities. Insiders.hk and Insiderslab.com have not been compensated by any of the above-mentioned companies. All calculated numbers or statistics are based on best effort. You hereby acknowledge that any reliance upon any Materials in this press release shall be at your sole risk. Please read our report and visit our Web sites, http://www.insiders.hk and http://www.insiderslab.com , for complete risks and disclosures.

Insider Filing Source Reference:
All observations are based on public information released by U.S. Securities and Exchange Commission.

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