World's 1st FPGA/CPLD Portal

ESL design software vendor CoWare Inc. and FPGA vendor Xilinx Inc. have signed an agreement under which CoWare is integrating and distributing models of Xilinx's LTE baseband IP portfolio with its SPW LTE solution.

I never thought I would be able to quote Karl Marx, the bearded philosopher, historian, revolutionary, and founder of communism, in an article on FPGAs, but here we go. “History repeats itself, first as tragedy, second as farce.” What I am thinking about is the way in which we design components. With ASICs and SoCs, we have seen a steady progression of increased abstraction in the EDA tools, from drawing the individual transistors as rectangles in the layers of silicon, up through schematic entry, through hardware description languages, to the emergence of today’s work on tools that describe entire systems. ESL (Electronic System Level) design is a good buzzword here, and we are seeing a lot of tools (plus a lot of smoke and mirrors) emerging in this domain. Tragedy is perhaps a harsh word to describe the evolution of these tools, but there haven’t been a lot of laughs in trying to ride Moore’s Law as process nodes get smaller and smaller and re-spins escalate into the stratosphere. ....

With today's modern FPGAs, designers are using sophisticated design methodologies that were once only used in the ASIC world. This includes the use of high level languages, RTL based design, and synthesis tools.

Synthesis is a critical step in translating high level descriptions of the design into a gate-level netlist that be used to implement the design using place-and-route tools. High level design methods and Synthesis tools are great time savers, and engineers also appreciate their optimization capabilities to find the best options for meeting power, timing and size requirements.

But sometimes things can get lost in translation.

In the process of transforming an RTL level design into a gate-level description, synthesis tools automatically make choices based on their internal optimization algorithms. Now, these optimization features are great for dealing with large complex designs. But engineers can be misled by the choices synthesis tools make as a result. The design may simulate fine. You may not see any warnings during synthesis, or more often you see huindreds of warnings - too many to sort through. But in the end, the design just doesn't work for some reason - a reason that you could spend days and weeks trying to uncover.

See, the synthesis engine makes assumptions about how to apply optimizations in response to different styles and inferred intent presented in your RTL. Without warning, RTL semantics may translate into structure that just doesn't work and you're left guessing what to change.

It can takes hours to re-run synthesis just to find out what to change, and hours again to change the synthesis parameters looking for the reason the tool did not map and optimize your design faithfully. That's if you know it broke your design... and if you don't, you have to add hours of place and route time mapping the broken design to the FPGA just to discover that something is wrong when you get to the lab.

There is a solution to this problem. Our RocketDrive® debug and verification solution bridges the gap between RTL and FPGA implementation by putting your FPGA into your simulator and giving you the tools you need to move back and forth between RTL and FPGA without guessing, re-synthesizing and re-routing. Finding issues caused by synthesis optimizations becomes simple with RocketDrive and doesn't require long loops through synthesis and routing each time you want to examine and debug different parts of the design.

So don't worry about your synthesis tool giving you fits and starts because something gets lost in translation. Let GateRocket be your FPGA ‘interpreter'. We can help you spell success in any language.

Actel Corp. on Thursday (Feb. 4) said that John East will retire as president and chief executive of the FPGA house and as a member of the board.

At the Consumer Electronics Show, Xilinx introduced the first market-specific Targeted Design Platform optimized for creating state-of-the-art digital television (DTV) solutions with the low-cost, low- power Xilinx Spartan-6 field programmable gate array (FPGA) family. DTV OEMs can now bring consumer digital displays to market quickly with high-definition picture quality and greater feature differentiation. For more information, visit Xilinx.

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FMC-XCLK2 quad channel clock generator on a FPGA mezzanine card (FMC/VITA 57) module features low jitter and phase-matched outputs

We all tend to have high levels of faith in various aspects of the FPGA design flow, but it's not long before we discover how unfounded this faith can be. In reality, bugs can manifest themselves in any portion of the FPGA design flow.

A few months ago I was at the Mexico city airport waiting for my flight departure and to kill time I

Australian design software vendor Altium unveiled a new version of its NanoBoard 3000 FPGA-based development board that features a Cyclone III FPGA from Altera.

We like our pictures. We like them to move and we like them to be sharp. We also want them in our pockets. Delivering high-quality video to mobile devices is truly a system-wide endeavor. Every link of the chain - from the heavy-iron infrastructure to the wireless access points to the mobile devices themselves require a major upgrade in bandwidth, compute performance, quality of service, and power efficiency. If you take your favorite market forecast and a spreadsheet, you can start with the number of subscribers and do the math back through the system - and come up with some sobering figures for bandwidth at every level. Today's 40G/100G challenges become tomorrows 400G challenges – and, with specifications and standards guaranteed to be in flux, this spells a big opportunity for programmable logic devices. ....

This article discusses the general issues of moving part, or all, of a DSP industrial application onto an FPGA using system software design tools. Using an FPGA and automated design software, design engineers have the ability to optimize system performance in ways not possible with a traditional DSP.

Altera today announced that its next-generation, 28nm devices will support partial reconfiguration. This means that Altera FPGA users will now be able to update small portions of an FPGA device, rather than having to re-synthesize, re-map and reprogram the entire device every time the application changes.

Xilinx has supported this feature for quite a few years, but has never made it a mainstream, supported feature of their ISE Design Suite development tools. However, in a recent email update to its customers, Xilinx announced with almost no fanfare that, in version 12 of the Xilinx tools, this important capability would finally be given its proper status as a supported feature. Perhaps the marketing department at Xilinx heard rumors coming from the other side of San Jose?

Corporate intrigue aside, this is an important piece of news. Why? Because software application developers first investigating FPGAs are surprised – even shocked – to learn how long the iteration times are for programming and debugging FPGA applications. And the larger the FPGA is, the worse the problem becomes.

For most software developers, being faced with the equivalent of a two, three, or even eight hour iteration time for compile-link-test is completely unacceptable, no matter how much potential increase in performance there may be.

And if, at the end of that long iteration time all the programmer has is a non-working, difficult-to-debug bitmap and a thousand-lines long report filled with hardware-esque warning messages? Then forget it. They might as well go use GPUs and CUDA.

So, why has it taken so long for this seemingly obvious feature to become mainstream? One can only assume that Xilinx and Altera management, their chip architects, and perhaps even their tools developers are hardware engineers first, and software engineers second. Perhaps they can only think of their devices as the poor-man’s ASIC. And their tools as a poor-man’s EDA.

Reliable, vendor-supported partial reconfiguration, including dynamic run-time reconfiguration, has the potential to solve so many problems for software application developers, and to broaden the market for FPGAs.

Consider:

Partial reconfiguration allows developers to iteratively recompile, re-synthesize, re-map and re-test a specific portion of the FPGA in just a few minutes, rather than a few hours. This in itself is a huge benefit. Instead of having to set up elaborate, hardware-oriented simulations to verify correct behavior before hitting that compile button, you can just try it out, again and again, in the same way you would when developing software. Indeed, this method of design was predominant for FPGAs in the 1980s and early 1990s. But as device densities have grown, iterative design-and-test methods have become impractical. That was good for the hardware simulator business, but bad for software developers.

Run-time reconfiguration allows certain parts of the FPGA to remain intact and functioning, for example the I/O processing, while other parts are being updated on-the-fly. Need to change the filtering of a video signal to respond to a change in resolution? Wham, it’s done, and so fast the viewer doesn’t even see a flicker. Want to change the FPGA’s function without causing a system reboot? How about leaving the PCIe endpoint alone and just changing the core algorithm?

Dynamic reconfiguration can increase the effective size of an FPGA. Loading of partial bitmaps at run-time allows the capacity of these devices to grow in the dimension of time. If you don’t need all the hardware capabilities you have programmed into your FPGA all the time, then use dynamic reconfiguration to swap hardware modules in and out as needed. Use reconfiguration to do more, with less.

Partial reconfiguration opens up new FPGA markets. Using partial reconfiguration, the vendors of FPGA-based platforms for specific types of applications – for financial transaction processing and automated trading, for example – could provide a “minimally programmable embedded system” in which most of the FPGA logic is pre-designed, pre-optimized and locked down, while a small portion in the middle is left available for end-user customization. This potentially opens up whole new application domains that were previously not available for FPGAs; applications in which the platform vendor and the end user both have unique domain knowledge, and have their own critical IP to protect.

Again, these capabilities are not really new; the Xilinx partial reconfiguration features have been used successfully, for years, in domains such as software-defined radio. What’s changing is that partial reconfiguration is finally becoming officially supported. With uncertainties about its future and its supportability reduced, software and platform vendors will now begin using these features to enable new programming, debugging and operating features into their own products.

It’s about time.

Altera today announced that its next-generation, 28nm devices will support partial reconfiguration. This means that Altera FPGA users will now be able to update small portions of an FPGA device, rather than having to re-synthesize, re-map and reprogram the entire device every time the application changes.

Xilinx has supported this feature for quite a few years, but has never made it a mainstream, supported feature of their ISE Design Suite development tools. However, in a recent email update to its customers, Xilinx announced with almost no fanfare that, in version 12 of the Xilinx tools, this important capability would finally be given its proper status as a supported feature. Perhaps the marketing department at Xilinx heard rumors coming from the other side of San Jose?

Corporate intrigue aside, this is an important piece of news. Why? Because software application developers first investigating FPGAs are surprised – even shocked – to learn how long the iteration times are for programming and debugging FPGA applications. And the larger the FPGA is, the worse the problem becomes.

For most software developers, being faced with the equivalent of a two, three, or even eight hour iteration time for compile-link-test is completely unacceptable, no matter how much potential increase in performance there may be.

And if, at the end of that long iteration time all the programmer has is a non-working, difficult-to-debug bitmap and a thousand-lines long report filled with hardware-esque warning messages? Then forget it. They might as well go use GPUs and CUDA.

So, why has it taken so long for this seemingly obvious feature to become mainstream? One can only assume that Xilinx and Altera management, their chip architects, and perhaps even their tools developers are hardware engineers first, and software engineers second. Perhaps they can only think of their devices as the poor-man’s ASIC. And their tools as a poor-man’s EDA.

Reliable, vendor-supported partial reconfiguration, including dynamic run-time reconfiguration, has the potential to solve so many problems for software application developers, and to broaden the market for FPGAs.

Consider:

Partial reconfiguration allows developers to iteratively recompile, re-synthesize, re-map and re-test a specific portion of the FPGA in just a few minutes, rather than a few hours. This in itself is a huge benefit. Instead of having to set up elaborate, hardware-oriented simulations to verify correct behavior before hitting that compile button, you can just try it out, again and again, in the same way you would when developing software. Indeed, this method of design was predominant for FPGAs in the 1980s and early 1990s. But as device densities have grown, iterative design-and-test methods have become impractical. That was good for the hardware simulator business, but bad for software developers.

Run-time reconfiguration allows certain parts of the FPGA to remain intact and functioning, for example the I/O processing, while other parts are being updated on-the-fly. Need to change the filtering of a video signal to respond to a change in resolution? Wham, it’s done, and so fast the viewer doesn’t even see a flicker. Want to change the FPGA’s function without causing a system reboot? How about leaving the PCIe endpoint alone and just changing the core algorithm?

Dynamic reconfiguration can increase the effective size of an FPGA. Loading of partial bitmaps at run-time allows the capacity of these devices to grow in the dimension of time. If you don’t need all the hardware capabilities you have programmed into your FPGA all the time, then use dynamic reconfiguration to swap hardware modules in and out as needed. Use reconfiguration to do more, with less.

Partial reconfiguration opens up new FPGA markets. Using partial reconfiguration, the vendors of FPGA-based platforms for specific types of applications – for financial transaction processing and automated trading, for example – could provide a “minimally programmable embedded system” in which most of the FPGA logic is pre-designed, pre-optimized and locked down, while a small portion in the middle is left available for end-user customization. This potentially opens up whole new application domains that were previously not available for FPGAs; applications in which the platform vendor and the end user both have unique domain knowledge, and have their own critical IP to protect.

Again, these capabilities are not really new; the Xilinx partial reconfiguration features have been used successfully, for years, in domains such as software-defined radio. What’s changing is that partial reconfiguration is finally becoming officially supported. With uncertainties about its future and its supportability reduced, software and platform vendors will now begin using these features to enable new programming, debugging and operating features into their own products.

It’s about time.

Synthesis tool vendor Synfora Inc. announced it has extended support for C++ language in its PICO Extreme and PICO Extreme FPGA C synthesis tools.

FPGA vendor Altera plans to introduce several innovations for its first 28-nm chips, including partial reconfiguration, 28-gigabit-per-second transceivers and embedded hard intellectual property blocks, the company said.

February and March are always busy months on the trade show calendar and 2010 is no different. The trade shows in our industry are usually a good way for designers to meet with suppliers and their partners face to face, hear about the latest trends, and learn some new things about design, tools, IP and the other aspects of making your jobs easier and better. In surveys, people usually rank peer-to-peer networking and word-of-mouth suggestion very highly on the list of how they get information to do their jobs, and that's why trade shows are still a good medium to bring together people with a common professional interest.

GateRocket will be participating in two events in February and March, one live and one virtual.

The first event is DVCon which has emerged as a preeminent show for engineers and management involved in the verification of ICs and systems. That's obviously right up our alley with our focus on improving how designers verify and debug complex FPGAs. DVCon is held Februrary 22-24 at the Doubletree Hotel in San Jose, near the airport. There are a lot of good sessions, tutorials, and panels planned and they all center on verification related issues. For GateRocket, we'll be using the show to take the wraps of some new technology in our latest release of our RocketVision and RocketDrive solutions. Can't reveal all the details yet but you can be assured we'll be delivering new ways to make verification and debug of FPGAs even more efficient. So if you can make it out to the event, be sure to stop by our booth #802.

The other event we'll be doing soon is called The FPGA Virtual Summit. As the name implies, it's not a live tradeshow like DVCon. It's an extended webinar, to be held March 18, that will consist of a series of presentations and discussions on various FPGA design topics. It's a neat format because you don't even have to leave the comfort of your own desk to take in the information - just log into the web site at the appointed time. It's interactive, too, so you can ask questions of the presenters. Granted, it's not quite the same as talking to someone live, but you can't beat the convenience. GateRocket will be participating in the FPGA Verification session in the afternoon and we'll be sending our more information shortly.

We hope you can join us at DVCon and The FPGA Virtual Summit in the coming weeks. We love hearing first hand from FPGA designers and both these events are ideal ways to do just that.

I recently spoke with Kapil Shankar, CEO of FPGA startup SiliconBlue Technologies, who told me the company now has over 100 design wins under its belt and will seek another round of financing in the next few months.

By building a three-dimensional field-programmable FPGA with an ultra-dense anti-fuse interconnect, NuPGA claims to be able to achieve the density of an ASIC at a fraction of the cost.

RMT announced it has been granted a patent titled "Virtual Hardware System with Universal Ports Using FPGA," which is the technology used in its Black Diamond Advanced Technology SwitchBack ultra-rugged mobile computer.