World's 1st FPGA/CPLD Portal

XLNX has some divergence MACD V’s price, Stochastics point to weakness ahead, Short if less than 26.66

ALTR may have some downward movement over the next few days, considering a short if price goes < 24.95

Nallatech's PCIe-180 targets 10-Gigabit Ethernet with Xilinx Virtex-5.

Probably you know that FPGA is pretty universal chip that can be programmed to do almost any task at high speed and efficiency. FPGA can do multiple tasks at in parallel so this makes it attractive in such designs where graphics manipulations are required.

In this project Cornell university students aimed to design programmable graphics processing unit that could do graphics transformations parametrically. This is tied to physics simulations where several objects could be manipulated in parametric level. This graphical processor has one pipeline where multiple pieces of data are operated in parallel. The design consists of three major parts: edge pipeline, transformation pipeline and rastering pipeline. This is quite complex stuff so more details in full project.

System level design is in the air. This is also true for motor control applications.

Up to now, this blog has mainly focused on commenting third-party articles relating to FPGA as a chip for embedded system development in power electronics applications, mostly for motor control. Unfortunately, most of those third-party articles have been written with an ”old” chip thinking comparing FPGA solely as another alternative to COTS DSP and MCUs. From a certain point of view this is completely understandable: those articles have been written by motor control people who have been using DSP since the last 15 years. Since the 90s, digital motor control embedded system design has been roughly the following: buy a DSP chip + plug it with other components on a PCB + program the DSP + plug your motor and check how is the motor running. Why it shouldn’t be the same with FPGAs in 2010 ?

The reason is because FPGAs are not a chip anymore: they are a platform. I am not inventing this, this is a reality. Xilinx’s CEO Moshe Gavrielov speaks about it, Altera’s CEO John Daane speaks about it specifically for Motor Control applications and so does Actel’s CEO John East.

What does this new kind of approach mean for motor control system applications ? The major shift here for motor control system design is not the semiconductor technology (FPGA) itself but the new level of component integration. I like to compare this shift to the one that happened in personnal computing: why smartphone are currently replacing PC ?

Old

New

System Platform

PC

iPhone

Components

Software

Apps

Component integration

Tideous

Easy

Flexibility

Low

High

Component cost (per unit, roughly)

25$-200$

1$-10$

Take a photo and share it over internet in 10 seconds from almost everywhere on the planet

Impossible.

Built-in.

On a component-to-component basis, it is true that my iPhone screen is not as convenient as my desktop screen, the email management software is not comparable to most desktop email management and the internet connection may not be as fast as a real cable internet connection. So if it is less perfomant, why does this happen ? This is not a question of performance, it’s a question of form factor. And this form factor enables you to do new things (with very high added-value) that were not possible on the former platform: like taking a photo and share it over internet from almost everywhere on the planet within 10 seconds. This is how Apple promotes its iPhone platform everywhere through the infinite uses of iPhone apps.

Is this situation comparable to FPGA-as-a-platform and its ecosystem of IP Cores (”apps”) ? In my opinion, it is:

Old

New

System Platform

PCB

FPGA

Components

IC (inluding FPGA)

IP

Component integration

Complex

Automatic

Flexibility

Low

High

Component cost

-

Lower

Design a complete system from scratch in one day

Impossible.

Yes.

In this new motor control embedded system design scheme, what was formerly a (PCB-integrated) motor control IC is now being replaced by a (FPGA-integrated) motor control IP (this is also true for other system-level IC such as image processing IC - see the excellent article of Kevin Morris - Paint-by-number ASSP ). Hence the question : what new things that a motor control IP can provide in motor control system applications over motor control IC ? Many of them are already mentionned in this Alizem Motor Control IP for Home Appliance applications white paper such as using reconfigurability of hardware to develop custom energy-optimal PWM. Here are some others :

Old

New

Motor Control component form factor

IC

IP

Quality

May vary

Constant

Supply

Limited

Unlimited

Lead time

Weeks-months

None

Component obsolesence

May happen.

No.

Motor Control application-specific

No – Generic

Yes – Specific

Integration with main controller

Tedious

Automatic

Component pin layout

Fixed

Customizable

Providing a motor control HW/SW upgrade service remotely to your customer at very low cost

Impossible. (HW upgrade involve chip replacement).

Its in the name (Field-Programmable) 

There’s is no doubt: there’s a worldwide growth to be expected in the coming years for power electronics applications: solar power, electric vehicule, smart-grid enabled industrial motor drive, etc.. But all this is going to happen in a business environment where great pressure is put on higher performance and reliability and lower costs and time-to-market. In those conditions, the FPGA plaform + Motor Control IP approach is certainly an option to consider to resolve those diverging constraints.

Pursuing with the “iPhone” analogy and considering IP as “apps” running on a FPGA platform, it is tempting to ask : will Altera, Xilinx and Actel - with their own IP ecology (”iStore”) - become the next ‘Apple’ of semiconductor space ? I look forward to hear the keynote “Future of FPGA Executive RoundTable: Key Element in your Design Future” tomorrow at the FPGA Virtual Summit.

I'm on a roll, and for my next blog I'd like us to turn our attention to how the synthesis engine may make unwarranted assumptions resulting in something ... unexpected.

Part on of a two-part article that focuses on the design guidelines and describes how to implement DDR or DDR2 external memory interfaces using FPGAs via ALTDLL and ALTDQ_DQS megafunctions.

Xilinx is among the finalists for the EE Times ACE Awards' Design Team of the Year honor.

Xilinx Inc. plans to demonstrate 40-gigabit optical transport network (OTN) developments for integrated multiplexer/transponder (muxponder) applications at next week's 2010 Optical Fiber Communication (OFC) conference and exposition, the company announced.

One of the problems of being an engineer is the compulsion to classify, count and measure things. Not just for professional purposes, but the sort of person who becomes an engineer seems also to be the sort of person who automatically counts, classifies and lists the things they encounter in everyday life. But some things are difficult to measure. Take love – Shakespeare's Mark Anthony proclaims that, “There's beggary in love that can be reckoned.” (Although, perhaps, Elizabeth Barrett Browning displays an engineering streak when she asks, “How do I love thee? Let me count the ways.”) Safety is another quality that does not lend itself to easy metrics, but it is something that has to be calibrated. We want our cars, our aeroplanes, our homes to be somehow “safe”, and the outcry after we feel we have been let down, as we can see today with the Toyota affair, is ample evidence that this is a general feeling. But the engineers who have to achieve that safety are faced with a vast range of conflicting pressures. If you were building a brand new transportation system, starting from a totally clean sheet of paper, is it socially acceptable to recognise that there is no such thing as absolute safety? At what point do you say, “It will cost $X million to make this safer and it will save one life a year”? ....

A couple of weeks after fabless chip startup Tabula Inc. tipped its time-sharing FPGA architecture the company has launched its ABAX family of chips. The company said the chips will sample in third quarter and go into mass production in Q4 2010.

We all know how much fun trade shows, seminars and technical conferences can be...the travel and time away from the office and important deadlines, the hours of sifting through oodles of content in order to find the relevant sessions to you, the pushy sales guys in flashy booths...Seriously, trade shows and conferences certainly serve their purpose in terms of learning about what is going on the industry, meeting peers, and general networking with suppliers, partners and some pretty smart people.

But a Virtual Conference is a great alternative as well. The folks at DSP.FPGA.com have put together a day-long event dedicated to FPGA design that you can take in from the comfort of your own desk. It's being held on Thursday, March 18 and all you have to do is register here and then log-in for the sessions you are interested in. It's all free of charge, and it's actually a live, interactive, online conference featuring experts from throughout the FPGA supply and design industries.

GateRocket will be featured in the Virtual Summit's Verification Track, describing how the latest innovations and improvements in our Version 5.0 of its RocketVision(R) debug and RocketDrive(R) verification solutions can improve designers' time to market with no changes to existing methodologies.

The Verification Track is being offered at 2:30PM (Eastern)/11:30AM (Pacific).

The FPGA Virtual Summit will have several separate tracks runing throughout the day, and so if you sign up, you can participate in any or all of them:

- 10AM: DSP Applications: Improve your DSP designs with FPGAs

- 11:30AM: FPGA Design Tools: Get your FPGA designs to market faster

- 2:30PM: FPGA Verification: Do you see what I see?

- 4:30PM: Keynote: Executive Round Table: The Future of FPGAs

Hope you can log-in and join us on the 18th - no airline or hotel reservation required!

 

Technology editor Bill Wong examines Actel’s new SmartFusion line of FPGAs that incorporate a hard core ARM Cortex-M3 and configurable analog peripherals.

Technology editor Bill Wong examines Actel’s new SmartFusion line of FPGAs that incorporate a hard core ARM Cortex-M3 and configurable analog peripherals.

National Semiconductor's LM3753 and LM3754 are full featured single-output dual-phase voltage-mode synchronous PWM buck controllers. They can be configured to control from 2 to 12 interleaved power stages creating a single high power output. Applications include: CPUs, GPUs (graphic cards), FPGAs, Large Memory Arrays, High Current POL Converters, Power Distribution Systems and more. For more information, visit National Semiconductor.

Hosted by: Don Tuite Videography by: Curtis Ellzey Edited by: Curtis Ellzey

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Lattice Semiconductor said it has now shipped more than 200 million ispMACH 4000 complex programmable logic devices.

Altera said its Stratix IV FPGAs passed the Interlaken Alliance's device interoperability testing, certifying that its FPGAs interface with third-party components using the Interlaken protocol.

Embedded software component provider Micrium announced that it has successfully ported its uC/OS-II and uC/OS-III kernels and uC/TCP-IP stack to Actel SmartFusion mixed-signal FPGA.

After getting some pretty good responses to a request for perspectives on Tabula, we are going to the well again to ask for reader responses to Actel's new SmartFusion family.

A little more than a week after long-simmering programmable logic startup Tabula emerged from stealth mode, Tier Logic stepped into the light to offer the first details about its technology, which employs a novel processing change to build FPGA and ASIC products on a single die.