Planet FPGA

Planet FPGA brings all the FPGA Blogs from around the web under one roof. So instead of visiting multiple blogs/portal to find updates on the blogs, just visit Planet FPGA and see all the updates together. You can visit the original blog post by clicking on the title of the blog post.
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What's New

FPGA From Scratch - Sven-Andersson - October 16, 2014 - 11:26pm
2014-10-08 Thank you all my readers. During the last 8 months you have visited my blog 49 000 times and looked at 150 000 pages.
2014-10-07 Adam Taylor is celebrating the first year anniversary of his Xcell Daily blog
2014-08-20 Restarting my blog
2014-07-18 Vacation time. No access to ZedBoard
2014-05-20 As you can see to the left, there is an advertisement added to my blog. Please contact me if your company would like to place an ad at the same place.
2014-05-18 I am going social. Share buttons have been added to Facebook, LinkedIn, Twitter and Google social networking sites.
2014-05-06 Clive Maxfield at EE Times writes about my blog once more.
2014-03-15 The Zynq blog has been added to the Xilinx Wiki.
2014-03-13 A link to my Zynq blog has been added in
2014-03-11 I have written an article for EE Times about my Zynq blog
2014-02-18 Xilinx writes about my Zynq blog
2014-02-10 ElektronikTidningen writes about my Zynq blog (in Swedish)
2014-02-06 Starting a new blog called "Zynq Design From Scratch"
2014-01-14 Updated

Categories: Planet FPGA

Impacts of an embedded software bug in power electronics applications

Distributed Feeds - October 8, 2014 - 8:04am

We all know software is a difficult skill to master and there are tremendous differences in developping software for:

  • PC/desktop applications
  • mobile/tablet applications
  • … and real-time embedded control applications such as power electronics applications

While in all cases a software bug may lead to important financial and human losses (directly or indirectly), the case of embedded software for power electronics application is special since it is meant to directly control the flow of energy from a source (battery, solar, etc.) to a load (electric motor, power network, etc.), not a flow of informations/signals/data is in a typical software application.

Impact #1: System component destruction

It means that a software bug may lead in the bad management of the flow of energy which can itself cause the destruction of components such as power stage (“shoot-through” faults), electric motor (“overcurrent” faults) or electric motor load (pump damage caused by cavitation for example).

impact of a bug power electronics software

Of course, proper installation of electrical equipement protection (i.e. fuses) can prevent most of the damage that may happen on the system components in case of a bug (overcurrent), but not all of them. For example, noise in a transducer may lead to torque ripple which may lead over time into electric motor bearing problems. This is the whole idea of electric motor “condition monitoring”, i.e. tracking over time the state of healt of the motor in order to : (1) detect faults (is there a fault, what component ?) and (2) diagnose faults (what is the cause of the fault, how severe the fault is). Those further interested in the subject may read this article.

Impact #2: Unique embedded motor control software development process

Hence, the development of motor control software needs not only software programming and digital signal processing skills, but it also needs deep “domain knowledge” experience related to power electronics, electric motors, transducers and the type of application where the software is going to run (in a home appliance or in an electric vehicle ?). More on this in a previous blog article. This point is not unique to power electronics software, the same could be same for embedded computer vision software (i.e. smart camera).

However, since motor control software bug may lead to component destruction, this has an impact on how the motor control software development and testing process is going to be made. Blowing a power stage is expensive and takes time to repair : it means you cannot afford to simply “develop some code and test” just like you would while developping a PC/mobile software application. It means you need to be sure that when you are going to turn the power switch on, you are not going to destroy your system.

How can you do that ? Well, you know my pitch on this.

The post Impacts of an embedded software bug in power electronics applications appeared first on PE-FPGA/

Categories: Planet FPGA

BBC Micro on FPGA

Distributed Feeds - September 19, 2014 - 3:35pm
"The project was, like the Spectrum, implemented on a Terasic DE1 board with an Altera Cyclone II FPGA. The entire design is written in VHDL, and it fits in 2907 logic elements when compiled on Quartus 9.1. This is about 16% of the capacity of the EP2C20. A small amount of on-chip memory is used for the teletext character generator ROM, with the program ROMs residing in off-chip flash."
Categories: Planet FPGA

How Do I FPGA? A Quick Intro

Distributed Feeds - August 31, 2014 - 8:42pm
"Not wanting to screw up an expensive complex board by being a first-timer at putting an FPGA into a circuit, I figured I’d build a little test board with the cheapest Spartan 6 you can get (about $10), which comes in a solderable TQFP144 package. Sadly, most high end FPGA’s are BGA and therefore quite hard to solder as a DIY project."
Categories: Planet FPGA

VHDL vs Verilog vs Schematic – New CPLD PyroEDU Lesson!

Distributed Feeds - August 28, 2014 - 11:35am
This week, we’re finishing off An Introduction to CPLD and FPGA with Lesson 10: VHDL vs Verilog vs Schematic. Here’s a short overview of the lesson:

"There are many ways to create a CPLD or FPGA image. The most common methods are with VHDL, Verilog or schematic capture. In this lesson we’ll explore and compare all three."

This online course is also be available through:
uReddit – P2PU
Categories: Planet FPGA

Only 8 Days Left!

Distributed Feeds - August 22, 2014 - 2:34pm
Just a reminder to all you Pyros out there: there are just 8 days left to enter the Pyro POV Contest! If you’re not sure how to build a POV device, no problem, PyroEDU has you covered! Check out our latest lesson Course 5: FPGA and CPLD » Lesson 9: Design a Handheld POV to learn how. Get those entries in soon for your chance to win a Basys2 Spartan-3E FPGA Development Board. Good luck!
Categories: Planet FPGA

Design a Handheld POV – New CPLD PyroEDU Lesson!

Distributed Feeds - August 21, 2014 - 7:54am
This week we’ll take a look at a very cool effect – persistence of vision in Lesson 9: Handheld LED POV. This is part of our new PyroEDU course: An Introduction to CPLD and FPGA. Here’s a short overview of the lesson:

"A very fascinating effect called persistence of vision can easily be created by repeatedly telling a single row of LEDs to output a message. Let’s build a POV with a secret message!"

This online course is also be available through:
uReddit – P2PU
Categories: Planet FPGA

Dimming LEDs via PWM – New CPLD PyroEDU Lesson!

Distributed Feeds - August 14, 2014 - 3:01pm
This week we’re moving onto a fun topic: Lesson 8: LED Dimming Via PWM where we’ll use PWM signals to control the brightness of some LEDs with VHDL code. This is part of our new PyroEDU course: An Introduction to CPLD and FPGA. Here’s a short overview of the lesson:

"We have used PWM in many other courses before, but creating PWM in an FPGA or CPLD requires a different way of thinking. Let’s make our own PWM output module to change the brightness of some LEDs. "

This online course is also be available through:
uReddit – P2PU
Categories: Planet FPGA

socz80: A Z80 retro Microcomputer Remade On A Spartan6 FPGA

Distributed Feeds - August 12, 2014 - 7:32am
"I built a small FPGA microcomputer for the Papilio Pro board. I’ve ported a few operating systems to run on it. These 8-bit machines have very minimal features but (somewhat unexpectedly) I found they can run a multi-user, multi-tasking UNIX operating system."
Categories: Planet FPGA

Parallel Hardware – New CPLD PyroEDU Lesson!

Distributed Feeds - August 7, 2014 - 11:35am
Did you know that FPGAs and CPLDs allow you to design hardware inside of them that operate entirely in parallel? This week, we explore this topic in Lesson 7: Parallel Hardware as part of our new PyroEDU course: An Introduction to CPLD and FPGA. Here’s a short overview of the lesson:

"A powerful tool of CPLD and FPGA design is being able to create multiple modules that perform operations in parallel. Let’s explore how this is done and why it is so awesome. "

This online course is also be available through:
uReddit – P2PU
Categories: Planet FPGA

Enter contest with your FPGA based POV

Distributed Feeds - August 5, 2014 - 7:29am

Pyroelectro announced that they started contest on building FPGA or CPLD based POV (Persistence Of Vision). There are plenty of microcontroller driven POV displays, clocks and 3D sculptures. FPGA’s can also be successfully used to build various types of POV’s.


Give a try and win prize (Basys2 Spartan-3E FPGA board). Submit your entry to [email protected] with the subject line “PyroElectro POV Contest.” Your entry must contain two photos of the device – one of its components in a well-lit environment and one of it in action in a darkened environment – as well as a circuit diagram and the VHDL code to run the device.

Categories: Planet FPGA

Design A Binary Timer In A CPLD – New PyroEDU Lesson!

Distributed Feeds - July 31, 2014 - 12:05pm
Timing and CPLDs is such an important idea that we dedicated a whole lesson to the topic. This week, we’re moving on to: Lesson 6: Design A Binary Timer as part of our new PyroEDU course: An Introduction to CPLD and FPGA. Here’s an overview of the lesson:

"We built a binary counter using all hardware components in the Digital Course, but now let’s build a binary counter by programming it using VHDL code."

This online course is also be available through:
uReddit – P2PU
Categories: Planet FPGA

ZX-Badaloc In A Spartan-3E FPGA

Distributed Feeds - July 26, 2014 - 10:51pm
"This project is aimed at synthesizing the ZX-Badaloc, a ZX-Spectrum Clone developed in Italy, into a Xilinx SPARTAN-3E Fpga. The original project’s main CPLD, I/O and Keyboard cplds, Z80 Processor, IDT dualport video ram can be squeezed into a single chip. This solves the main problem: WIRINGS."
Categories: Planet FPGA

Pyro POV Contest

Distributed Feeds - July 25, 2014 - 8:15am
We are excited to announce a new contest we will be hosting over the next several weeks!

Build your very own electronic device to demonstrate Persistence of Vision (POV) using an FPGA or CPLD. Visit the Contest Page for details on how to enter, prizes, and more. Also, visit the Pyro Propeller Clock POV Project to get an idea what POV is. If you’re unsure how to build one, don’t worry! PyroEDU’s 5th Course: FPGA and CPLD will soon cover how to build your own handheld POV device, just in time to build one before the contest ends on August 30th, 2014. Good luck!
Categories: Planet FPGA

Procedural Logic And FPGAs + CPLDs- New PyroEDU Lesson!

Distributed Feeds - July 24, 2014 - 11:35am
This week we’re moving on to Lesson 5: Procedural Logic, a topic that moves simple combinatorial logic to add clocking! This lesson is part of our new PyroEDU course: An Introduction to CPLD and FPGA. Here’s an overview of the lesson:

"FPGA and CPLD devices offer a separate type of logic which happens in series. This is called procedural logic and it uses a clock source to drive the logic contained within the procedure."

This online course is also be available through:
uReddit – P2PU
Categories: Planet FPGA

Using the DP Bus Blaster v3c to program Lattice CPLDs

Distributed Feeds - July 23, 2014 - 3:37pm
"One day when playing with the CPLD board I accidentally shorted out two pins on the on-board FT2232 and – unfortunately – the magic smoke escaped! It was very clear that the FT2232 failed because it got very warm when plugging in the USB cable. Luckily the dev kit includes a 0.1″ header landing to connect an external JTAG probe. Wanting to get a Dangerous Prototypes Bus Blaster JTAG programmer anyway, this was the perfect excuse."
Categories: Planet FPGA

D.I.Y. Sega Genesis Cartridge UMDKv2 (FPGA)

Distributed Feeds - July 22, 2014 - 3:00pm
"The UMDKv2 is basically a PROM emulator. It’s a small FPGA board connected to a USB MegaDrive Kit. UMDKv1 (link) Is also worth a look, it uses an AVR microcontroller as a PROM emulator."
Categories: Planet FPGA

FPGAs, CPLDs and Combinatorial Logic – New PyroEDU Lesson!

Distributed Feeds - July 17, 2014 - 12:15pm
The topic for this week’s lesson in FPGA and CPLD land is: Lesson 4: Combinatorial Logic. This lesson is part of our new PyroEDU course: An Introduction to CPLD and FPGA. Here’s an overview of the lesson:

"In the Introduction to Digital Electronics course, we explored AND, OR, NOT, NOR and other logic gates. Now we’ll harness the power of programmed logic to dynamically create and use these gates in a CPLD."

This online course is also be available through:
uReddit – P2PU
Categories: Planet FPGA

Copy Protection in Modern Microcontrollers

Distributed Feeds - July 16, 2014 - 12:42am
"This article is based on the research made between 1996 and 2000. The past ten years of my research into hardware security showed that any microcontroller, FPGA, secure memory, smartcard, ASIC or custom chip can be successfully attacked given enough time and resources. The question is whether the semiconductor chip used in a particular application can withstand multi-million-dollar attack or would fail to defeat a 10-dollar attack."
Categories: Planet FPGA

Parallel port jtag

Distributed Feeds - July 11, 2014 - 2:45pm
I've been using a homebrew version of the Xilinx DLC5 parallel port jtag adapter for programming my fpga boards. The DLC5 is no longer supported by Xilinx, but some Linux jtag programmers still support it.
Recently I moved to a new PC, and my DLC5 hack no longer works with that parallel port. I can see on the scope that the right pins are moving, but the chip won't program. I suspect that either the rise and fall times are too slow, or there's noise on the signal lines.
Anyway, I had a sample of the SiLabs si8663 digital isolator, so I decided it's time to build a new interface. The Si8663 is a hex isolator (3 signals each direction), that's spec'ed to operate up to 150 Mbps bit rate (WAY more than needed for this app). Another neat feature is that the drivers on each side work from 2.5 to 5.5 volts, providing a level shifter at no extra charge.
Board is available on OshPark ( for anyone interested. Project name is "isopartag 140513". Circuit's simple: chip + 4 bypass caps on the bottom. The design includes resistors to tap power from unused pins of the parallel port, but they haven't been added yet, to that feature is untested. For now I just tap 5 volts from an unused keyboard or mouse port.
Caution:The Si8663 comes in two versions: a wide body for safety isolation, and a narrow body intended more for electrical noise isolation. I'm using the narrow version, and the board is not designed with wide separation between the input and output sides. In other words, this design is for low voltages only, don't use it where safety is an issue.
Categories: Planet FPGA

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