Planet FPGA

Planet FPGA brings all the FPGA Blogs from around the web under one roof. So instead of visiting multiple blogs/portal to find updates on the blogs, just visit Planet FPGA and see all the updates together. You can visit the original blog post by clicking on the title of the blog post.
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Intro to FPGA and CPLD: Lesson 3 Live!

Distributed Feeds - 8 hours 51 min ago
This week we’re moving on to Lesson 3: Input & Output in our new PyroEDU course: An Introduction to CPLD and FPGA. Here’s an overview of the lesson:

"All FPGA and CPLD devices have general purpose input and output pins, often called GPIO. Here we will take a look at how to build a CPLD image and hardware to accept push-button input in order to affect output LEDs."

This online course is also be available through:
uReddit – P2PU
Categories: Planet FPGA

Intro to FPGA and CPLD: Lesson 2 Live!

Distributed Feeds - July 3, 2014 - 12:40pm
This week we’re moving on to Lesson 2: Hardware Hello world in our new PyroEDU course: An Introduction to CPLD and FPGA. Here’s an overview of the lesson:

"Building a ‘hello world’ application signifies a time honored approach to learning how to program. In this lesson, we will explore the first steps necessary for building and loading images onto a CPLD."

This online course is also be available through:
uReddit – P2PU
Categories: Planet FPGA

Xilinx Spartan-3 I/O timing

Distributed Feeds - June 30, 2014 - 2:02am
Working on updating the MHZ100Q project, and one significant design issue is I/O delay. To review, the Xilinx Spartan-3A FPGA generates a 100MHz clock using an internal DCM block, and this clock drives an external 100MHz A/D converter. The total delays through the output buffer, A/D clock to output pins, and FPGA input buffer add up to 9 to 16 ns, while the clock cycle time is 10 ns. So aligning the clock and data at the input latch is tricky.
Per the A/D data sheet, the value on the output pins is stable for about 5ns (minimum) and the FPGA data sheet says the latches need about 1ns to capture the value (setup+hold times from the clock edge). So we have a 4 ns window in which everything will work right.
It's hard to measure the actual offset at the internal latch input of the FPGA, so for initial setup I would like to be able to adjust the phasing of the A/D clock relative to the internal latch clock over the full 10 ns range.
First option is to use the built-in delays. The *.ucf file supports the per-pin specifications IFD_DELAY_VALUE and IBUF_DELAY_VALUE which put variable amounts of delay between the input pin and the logic (the former applies when using the latch built-in to the I/O Block, and the latter applies when the I/O Block is just used as a buffer). Total adjustment range is about 2 ns, which might be enough.
Next step up in complexity is to use the Digital Clock Module (DCM) to adjust the phase of the generated clock. The DCM can produce essentially any clock phase, but for this application, I think I can just use the 4-phase quadrature outputs. That gives me effectively 0 2.5, 5, 7.5 ns adjustment points, and combined with the IFD_DELAY_VALUE, I can get within 0.5 ns of any required timing offset.
Categories: Planet FPGA

CPLD Programming: What is JTAG?

Distributed Feeds - June 29, 2014 - 9:02am
"Here we will discuss The ‘JTAG’ IEEE 1532 standard used for ‘ISP’ (In-System-Programming) I will also talk about Atmel’s ‘AVR ISP’ programmer and it’s ‘SPI’ (Serial-Peripheral-Interface)."
Categories: Planet FPGA

Hello world with CPLD and FPGA

Distributed Feeds - June 28, 2014 - 6:52am

CPLD and FPGA are different from microcontroller concept. Instead of writing programs here you need to configure hardware. With modern tools and programming languages like VHDL or Verilog things are much easier. Pyroelectro has started a series of tutorials where you will lean the very basics of building your own projects with CPLD and so with FPGA. This one is dedicated to turning LED on and off.

There are a list of courses to come where you will learn more advanced topics that will allow to feel the benefit of using CPLD over microcontrollers.

Categories: Planet FPGA

Intro to FPGA and CPLD: Lesson 1 Live!

Distributed Feeds - June 26, 2014 - 11:35am
Today we’re happy to announce that lesson 1 of our new course: An Introduction To FPGA And CPLD is live. Here’s an overview of the lesson:

"Want to learn about FPGA and CPLD? Please start here! This lesson explains the course content, what expectations you should have and what parts are needed for the course."

This online course is also be available through:
uReddit – P2PU
Categories: Planet FPGA

PyroEDU: An Introduction To FPGA And CPLD (Starts June 26th)

Distributed Feeds - June 23, 2014 - 3:41pm
Thanks to continued support and feedback from all of YOU, we are excited to announce that the 5th course of PyroEDU: An Introduction To FPGA And CPLD will begin this week! Here’s a preview of the course overview:

“This course is meant to create a pathway into learning about FPGA and CPLD electronics, for people who are scared of the code, tools and general trickery that usually comes with it. A hands-on approach is taken in this course through a combination of lecture and experimentation to teach you about the different features of both the development tools and languages used in the world of FPGA. Additionally, visuals are used throughout lectures like step-by-step schematic building and line-by-line code explanations so that everything gets explained.”

This course comes right on the heels of An Introduction To Microcontrollers and as such, it will use knowledge from that course to further expand to the world of programmed logic and hardware. Also, thanks again to all of our kickstarter backers who originally got us started! Read more at the course page at PyroEDU This online course will also be available through:
uReddit – P2PU
Categories: Planet FPGA

What's New

FPGA From Scratch - Sven-Andersson - June 22, 2014 - 11:26pm
2014-05-20 As you can see to the left, there is an advertisement added to my blog. Please contact me if your company would like to place an ad at the same place.
2014-05-18 I am going social. Share buttons have been added to Facebook, LinkedIn, Twitter and Google social networking sites.
2014-05-06 Clive Maxfield at EE Times writes about my blog once more.
2014-03-15 The Zynq blog has been added to the Xilinx Wiki.
2014-03-13 A link to my Zynq blog has been added in
2014-03-11 I have written an article for EE Times about my Zynq blog
2014-02-18 Xilinx writes about my Zynq blog
2014-02-10 ElektronikTidningen writes about my Zynq blog (in Swedish)
2014-02-06 Starting a new blog called "Zynq Design From Scratch"
2014-01-14 Updated

Categories: Planet FPGA

e8051 high speed 8051 cores

Distributed Feeds - June 15, 2014 - 6:57am
The e8051 is the fastest available 8051/8052 embedded microcontroller core for ASICs and FPGAs, achieving peak processing speeds of up to 300 Mips in ASICs and up to or above 130 Mips in FPGAs (equivalent to 3.6 GHz/1.5 GHz clock rates in a conventional 8051) e8051 high speed 8051 cores A free evaluation kit download is available for running small test programs at full speed in the user's own
Categories: Planet FPGA

Xilinx CPLD Board Electronic Project

Distributed Feeds - June 5, 2014 - 5:09pm
"Build this single-sided Xilinx CPLD board at home and experiment with CPLDs and hardware description language (HDL). The source files for the project are in open source KiCad format so you can modify the circuit diagram and PCB if needed."
Categories: Planet FPGA

Xilinx UltraScale SelectIO CTLE Demo includes ADS Simulations

Distributed Feeds - May 14, 2014 - 9:22am
Thanks to Romi Mayder and Ravindra Gali for including screen shots of their ADS simulations in this video demo of the continous time linear equalizer (CTLE) in the SelectIO of the UltraScale chip.
Categories: Planet FPGA

Xilinx and Agilent DDR4 at 2400 Mb/s for JEDEC Compliance

Distributed Feeds - April 18, 2014 - 6:52am

Thanks to Xilinx for this video clip featuring my colleague Ai-Lee Grumbine demonstrating our DDR4 compliance app on their demo board with the UltraScale 2400Mb/s DDR4 controller. (Please be patient: the video stream takes a few seconds to buffer.)

Categories: Planet FPGA

Spartan 6 – FPGA Based Bus Pirate

Distributed Feeds - April 16, 2014 - 8:20am
"A FPGA based design with a soft CPU and USB device interface implemented in Verilog. A small USB stack implements a virtual serial port over USB, but could be extended to support other class drivers such as Audio or HID. This board is form factor compatible with the Bus Pirate v3.5 case"
Categories: Planet FPGA

tPad Embedded System: the 2048 game + Draw Picture

Distributed Feeds - April 10, 2014 - 10:11pm

This time, we had an advanced version of FPGA project (comparing to Color Piano), which involving touch panel, gravity sensor and VGA screen.  It was also an embedded system design, that could had more functions and more adaptivity  than implying the hardware alone.

The system was first designed with only the “start” screen and the “touch-draw” function last year. Then we added the fun game “2048″, to make it more fun.

  • The old tPad project.

We had this tPad project one year ago in the advance VLSI design class. The we tried embedded system for the following reasons:

  1. We could have software in the project, like programming in C, other than Verilog alone.
  2. The hardware design could be separated with the software function.
  3. Highly adaptivity and easier to add more functions.

We started building the hardware frame by using SPOC builder from the Quartus II. Adding the CPU, JTAG, CFI Flash, SDRAM, PLL, ADXL345, I2C and the LCD screen and other components.

Then we added a Power Manage Unit in the hardware to realize the function of “saving power”, which was turning off the screen if the screen was not touched for 10 seconds (we made it 3 seconds in the video demonstration).

Luckily the Altera had provided the drivers for all the hardware components, and we could directly use those drivers.

We realized the “draw” function by collecting the dots that we touched on the screen. And you could choose different colors and clear the previous screen. You could also clear the screen by shaking it.

The glitches in the video are caused by 2 major reasons: 1. The screen is a resistive touch screen, it is less accurate than the capacitance touch screen. 2. We lowered the frequency of getting the position of dots. So when I moved quickly on the screen, the dots were more “discrete”

  • The 2048 game

This presentation was the 2048 game alone.

When we were wrapping the previous projects, the fun game 2048 ( ) was launched,  and we started the idea of making it into out tPad system.  We chose the gravity sensor as the input instead of  arrow keys. You could also choose to restart the game by touch the “Clear” button.

  • Integrated Together

From this “integrated” system that we can choose which the sub program to run and return to the start menu, as the video in the beginning.

Categories: Planet FPGA

CPLD Tutorial: Learn Programmable Logic the Easy Way

Distributed Feeds - April 6, 2014 - 4:01am


The guys over at hackshed have been busy. [Carl] is making programmable logic design easy with an 8 part CPLD tutorial. Programmable logic devices are one of the most versatile hardware building blocks available to hackers. They also can have a steep learning curve. Cheap Field Programmable Gate Arrays (FPGA) are plentiful, but can have intricate power requirements. Most modern programmable logic designs are created in a Hardware Description Language (HDL) such as VHDL or Verilog. Now you’ve got a new type of device, a new language, an entirely new programming paradigm, and a complex IDE to learn all at once. It’s no wonder FPGAs have sent more than one beginner running for the hills.

The tutorial cuts the learning curve down in several ways. [Carl] is using Complex Programmable Logic Devices (CPLD). At the 40,000 foot level, CPLDs and FPGAs do the same thing – they act as re-configurable logic. FPGAs generally do not store their configuration – it has to be loaded from an external FLASH, EEPROM, or connected processor. CPLDs do store their configuration, so they’re ready as soon as they power up. As a general rule, FPGAs contain more configurable logic than CPLDs. This allows for larger designs to be instantiated with FPGAs. Don’t knock CPLDs though. CPLDs have plenty of room for big designs, like generating VGA signals.

[Carl] also is designing with schematic capture in his tutorial. With the schematic capture method, digital logic schematics are drawn just as they would be in Eagle or KiCad. This is generally considered an “old school” method of design capture. A few lines of VHDL or Verilog code can replace some rather complex schematics. [Carl's] simple designs don’t need that sort of power though. Going the schematic capture route eliminates the need to learn VHDL or Verilog.

[Carl's] tutorial starts with installing Altera’s Quartus II software. He then takes the student through the “hardware hello world” – blinking an LED.  By the time the tutorial is done, the user will learn how to create a 4 bit adder and a 4 bit subtractor. With all that under your belt, you’re ready to jump into big designs – like building a retrocomputer.

[Image via Wikimedia Commons]

Categories: Planet FPGA

Color Piano

Distributed Feeds - April 3, 2014 - 9:54pm

Color Piano is a FPGA board project that can recognize different color and play the sound through camera input. Our piano dose not have the ordinary keyboard as input, instead we decide to use camera as the input to get the signal of different colors. This Color Piano can play 7 different notes (from middle C to B), with corresponding green LED lights indicate the notes, and red LED lights for the RGB value of every pixel (approximately). This project can be the prototype of some projects that has more function as an electronic keyboard instrument like recording, beat generation and mix.

My partner and I designed a FPGA system on an Altera’s DE2-70 board with Cyclone II 2C70 FPGA and 5 megapixel resolution TRBD_D5M camera as input, led lights and headphone as outputs.

Using Quartus II to synthesis Verilog code and build the system that could recognize different colors through the on board real-time camera input and play corresponding sounds through a headphone that was linked to an IO pin generates the sound frequency signal.

Here is a figure for the normalization of the image signal.Screen Shot 2014-04-03 at 1.52.30 PM


Feel free to leave any comments or contact me: [email protected]


Categories: Planet FPGA

Beginning FPGAs

Distributed Feeds - March 31, 2014 - 10:36am
Categories: Planet FPGA

How to Get into FPGA

Distributed Feeds - March 25, 2014 - 12:52pm
The FPGA business is growing at a rapid pace and so is the technology. A bachelor’s degree in electr
Categories: Planet FPGA

FPGA NES Using Xilinx Spartan3

Distributed Feeds - March 23, 2014 - 11:06am
"Behold: a complete Nintendo Entertainment System cloned in an FPGA! Originally written in VHDL by Brent Allen and myself while at Washington State University, I’ve recently revisited this project and begun both: rewriting it in Verilog, and adding many new features."
Categories: Planet FPGA

DIY Xilinx Parallel Cable III

Distributed Feeds - March 22, 2014 - 12:59pm
"This is a simple JTAG interface, which can be connected to computer’s parallel port. It is originally designed by Xilinx to program FPGAs and CPLDs… It is a one-sided PCB, the bottom side is made from wires."
Categories: Planet FPGA

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