Planet FPGA

Planet FPGA brings all the FPGA Blogs from around the web under one roof. So instead of visiting multiple blogs/portal to find updates on the blogs, just visit Planet FPGA and see all the updates together. You can visit the original blog post by clicking on the title of the blog post.
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Pyro POV Contest

Distributed Feeds - 5 hours 19 min ago
We are excited to announce a new contest we will be hosting over the next several weeks!

Build your very own electronic device to demonstrate Persistence of Vision (POV) using an FPGA or CPLD. Visit the Contest Page for details on how to enter, prizes, and more. Also, visit the Pyro Propeller Clock POV Project to get an idea what POV is. If you’re unsure how to build one, don’t worry! PyroEDU’s 5th Course: FPGA and CPLD will soon cover how to build your own handheld POV device, just in time to build one before the contest ends on August 30th, 2014. Good luck!
Categories: Planet FPGA

Procedural Logic And FPGAs + CPLDs- New PyroEDU Lesson!

Distributed Feeds - July 24, 2014 - 11:35am
This week we’re moving on to Lesson 5: Procedural Logic, a topic that moves simple combinatorial logic to add clocking! This lesson is part of our new PyroEDU course: An Introduction to CPLD and FPGA. Here’s an overview of the lesson:

"FPGA and CPLD devices offer a separate type of logic which happens in series. This is called procedural logic and it uses a clock source to drive the logic contained within the procedure."

This online course is also be available through:
uReddit – P2PU
Categories: Planet FPGA

Using the DP Bus Blaster v3c to program Lattice CPLDs

Distributed Feeds - July 23, 2014 - 3:37pm
"One day when playing with the CPLD board I accidentally shorted out two pins on the on-board FT2232 and – unfortunately – the magic smoke escaped! It was very clear that the FT2232 failed because it got very warm when plugging in the USB cable. Luckily the dev kit includes a 0.1″ header landing to connect an external JTAG probe. Wanting to get a Dangerous Prototypes Bus Blaster JTAG programmer anyway, this was the perfect excuse."
Categories: Planet FPGA

D.I.Y. Sega Genesis Cartridge UMDKv2 (FPGA)

Distributed Feeds - July 22, 2014 - 3:00pm
"The UMDKv2 is basically a PROM emulator. It’s a small FPGA board connected to a USB MegaDrive Kit. UMDKv1 (link) Is also worth a look, it uses an AVR microcontroller as a PROM emulator."
Categories: Planet FPGA

What's New

FPGA From Scratch - Sven-Andersson - July 17, 2014 - 11:26pm
2014-07-18 Vacation time. No access to ZedBoard
2014-05-20 As you can see to the left, there is an advertisement added to my blog. Please contact me if your company would like to place an ad at the same place.
2014-05-18 I am going social. Share buttons have been added to Facebook, LinkedIn, Twitter and Google social networking sites.
2014-05-06 Clive Maxfield at EE Times writes about my blog once more.
2014-03-15 The Zynq blog has been added to the Xilinx Wiki.
2014-03-13 A link to my Zynq blog has been added in ZedBoard.org
2014-03-11 I have written an article for EE Times about my Zynq blog
2014-02-18 Xilinx writes about my Zynq blog
2014-02-10 ElektronikTidningen writes about my Zynq blog (in Swedish)
2014-02-06 Starting a new blog called "Zynq Design From Scratch"
2014-01-14 Updated wildskating.com


Categories: Planet FPGA

FPGAs, CPLDs and Combinatorial Logic – New PyroEDU Lesson!

Distributed Feeds - July 17, 2014 - 12:15pm
The topic for this week’s lesson in FPGA and CPLD land is: Lesson 4: Combinatorial Logic. This lesson is part of our new PyroEDU course: An Introduction to CPLD and FPGA. Here’s an overview of the lesson:

"In the Introduction to Digital Electronics course, we explored AND, OR, NOT, NOR and other logic gates. Now we’ll harness the power of programmed logic to dynamically create and use these gates in a CPLD."

This online course is also be available through:
uReddit – P2PU
Categories: Planet FPGA

Copy Protection in Modern Microcontrollers

Distributed Feeds - July 16, 2014 - 12:42am
"This article is based on the research made between 1996 and 2000. The past ten years of my research into hardware security showed that any microcontroller, FPGA, secure memory, smartcard, ASIC or custom chip can be successfully attacked given enough time and resources. The question is whether the semiconductor chip used in a particular application can withstand multi-million-dollar attack or would fail to defeat a 10-dollar attack."
Categories: Planet FPGA

Parallel port jtag

Distributed Feeds - July 11, 2014 - 2:45pm
I've been using a homebrew version of the Xilinx DLC5 parallel port jtag adapter for programming my fpga boards. The DLC5 is no longer supported by Xilinx, but some Linux jtag programmers still support it.
Recently I moved to a new PC, and my DLC5 hack no longer works with that parallel port. I can see on the scope that the right pins are moving, but the chip won't program. I suspect that either the rise and fall times are too slow, or there's noise on the signal lines.
Anyway, I had a sample of the SiLabs si8663 digital isolator, so I decided it's time to build a new interface. The Si8663 is a hex isolator (3 signals each direction), that's spec'ed to operate up to 150 Mbps bit rate (WAY more than needed for this app). Another neat feature is that the drivers on each side work from 2.5 to 5.5 volts, providing a level shifter at no extra charge.
Board is available on OshPark (www.oshpark.com) for anyone interested. Project name is "isopartag 140513". Circuit's simple: chip + 4 bypass caps on the bottom. The design includes resistors to tap power from unused pins of the parallel port, but they haven't been added yet, to that feature is untested. For now I just tap 5 volts from an unused keyboard or mouse port.
Caution:The Si8663 comes in two versions: a wide body for safety isolation, and a narrow body intended more for electrical noise isolation. I'm using the narrow version, and the board is not designed with wide separation between the input and output sides. In other words, this design is for low voltages only, don't use it where safety is an issue.
Categories: Planet FPGA

Intro to FPGA and CPLD: Lesson 3 Live!

Distributed Feeds - July 10, 2014 - 11:35am
This week we’re moving on to Lesson 3: Input & Output in our new PyroEDU course: An Introduction to CPLD and FPGA. Here’s an overview of the lesson:

"All FPGA and CPLD devices have general purpose input and output pins, often called GPIO. Here we will take a look at how to build a CPLD image and hardware to accept push-button input in order to affect output LEDs."

This online course is also be available through:
uReddit – P2PU
Categories: Planet FPGA

Cheaper FPGA boards are getting closer

Distributed Feeds - July 9, 2014 - 9:41am

Michael Dunn have done a research on FPGA boards available for less than $100. We all know that hobby market is always looking for low price hardware to do amazing projects. We already have almost free microcontroller boards including 8-bit and 32-bit ARM. FPGA always were was behind barrier. Not things seems to changing.

AltDE0

Today you can get quit several FPGA boards for your projects that are under $100 limit. You can find boards from Altera, Cypress, Lattice, Microsemi, Xilink and even more that aren’t listed. The lowest price you can find is like $4 for PSoC 4 FPGA board (at least more or less). In that price range you can get up to 22 kLE (logic elements). This is more than enough to run soft processor, build calculus intense projects like signal generators, scopes, signal processing modules and other projects where microcontrollers wouldn’t have enough juice. It takes some learning to get used to them, but there is quite enough tutorials to get started.

Categories: Planet FPGA

Intro to FPGA and CPLD: Lesson 2 Live!

Distributed Feeds - July 3, 2014 - 12:40pm
This week we’re moving on to Lesson 2: Hardware Hello world in our new PyroEDU course: An Introduction to CPLD and FPGA. Here’s an overview of the lesson:

"Building a ‘hello world’ application signifies a time honored approach to learning how to program. In this lesson, we will explore the first steps necessary for building and loading images onto a CPLD."

This online course is also be available through:
uReddit – P2PU
Categories: Planet FPGA

Xilinx Spartan-3 I/O timing

Distributed Feeds - June 30, 2014 - 2:02am
Working on updating the MHZ100Q project, and one significant design issue is I/O delay. To review, the Xilinx Spartan-3A FPGA generates a 100MHz clock using an internal DCM block, and this clock drives an external 100MHz A/D converter. The total delays through the output buffer, A/D clock to output pins, and FPGA input buffer add up to 9 to 16 ns, while the clock cycle time is 10 ns. So aligning the clock and data at the input latch is tricky.
Per the A/D data sheet, the value on the output pins is stable for about 5ns (minimum) and the FPGA data sheet says the latches need about 1ns to capture the value (setup+hold times from the clock edge). So we have a 4 ns window in which everything will work right.
It's hard to measure the actual offset at the internal latch input of the FPGA, so for initial setup I would like to be able to adjust the phasing of the A/D clock relative to the internal latch clock over the full 10 ns range.
First option is to use the built-in delays. The *.ucf file supports the per-pin specifications IFD_DELAY_VALUE and IBUF_DELAY_VALUE which put variable amounts of delay between the input pin and the logic (the former applies when using the latch built-in to the I/O Block, and the latter applies when the I/O Block is just used as a buffer). Total adjustment range is about 2 ns, which might be enough.
Next step up in complexity is to use the Digital Clock Module (DCM) to adjust the phase of the generated clock. The DCM can produce essentially any clock phase, but for this application, I think I can just use the 4-phase quadrature outputs. That gives me effectively 0 2.5, 5, 7.5 ns adjustment points, and combined with the IFD_DELAY_VALUE, I can get within 0.5 ns of any required timing offset.
Categories: Planet FPGA

CPLD Programming: What is JTAG?

Distributed Feeds - June 29, 2014 - 9:02am
"Here we will discuss The ‘JTAG’ IEEE 1532 standard used for ‘ISP’ (In-System-Programming) I will also talk about Atmel’s ‘AVR ISP’ programmer and it’s ‘SPI’ (Serial-Peripheral-Interface)."
Categories: Planet FPGA

Hello world with CPLD and FPGA

Distributed Feeds - June 28, 2014 - 6:52am

CPLD and FPGA are different from microcontroller concept. Instead of writing programs here you need to configure hardware. With modern tools and programming languages like VHDL or Verilog things are much easier. Pyroelectro has started a series of tutorials where you will lean the very basics of building your own projects with CPLD and so with FPGA. This one is dedicated to turning LED on and off.

There are a list of courses to come where you will learn more advanced topics that will allow to feel the benefit of using CPLD over microcontrollers.

Categories: Planet FPGA

Intro to FPGA and CPLD: Lesson 1 Live!

Distributed Feeds - June 26, 2014 - 11:35am
Today we’re happy to announce that lesson 1 of our new course: An Introduction To FPGA And CPLD is live. Here’s an overview of the lesson:

"Want to learn about FPGA and CPLD? Please start here! This lesson explains the course content, what expectations you should have and what parts are needed for the course."

This online course is also be available through:
uReddit – P2PU
Categories: Planet FPGA

PyroEDU: An Introduction To FPGA And CPLD (Starts June 26th)

Distributed Feeds - June 23, 2014 - 3:41pm
Thanks to continued support and feedback from all of YOU, we are excited to announce that the 5th course of PyroEDU: An Introduction To FPGA And CPLD will begin this week! Here’s a preview of the course overview:

“This course is meant to create a pathway into learning about FPGA and CPLD electronics, for people who are scared of the code, tools and general trickery that usually comes with it. A hands-on approach is taken in this course through a combination of lecture and experimentation to teach you about the different features of both the development tools and languages used in the world of FPGA. Additionally, visuals are used throughout lectures like step-by-step schematic building and line-by-line code explanations so that everything gets explained.”

This course comes right on the heels of An Introduction To Microcontrollers and as such, it will use knowledge from that course to further expand to the world of programmed logic and hardware. Also, thanks again to all of our kickstarter backers who originally got us started! Read more at the course page at PyroEDU This online course will also be available through:
uReddit – P2PU
Categories: Planet FPGA

e8051 high speed 8051 cores

Distributed Feeds - June 15, 2014 - 6:57am
The e8051 is the fastest available 8051/8052 embedded microcontroller core for ASICs and FPGAs, achieving peak processing speeds of up to 300 Mips in ASICs and up to or above 130 Mips in FPGAs (equivalent to 3.6 GHz/1.5 GHz clock rates in a conventional 8051) e8051 high speed 8051 cores A free evaluation kit download is available for running small test programs at full speed in the user's own
Categories: Planet FPGA

Xilinx CPLD Board Electronic Project

Distributed Feeds - June 5, 2014 - 5:09pm
"Build this single-sided Xilinx CPLD board at home and experiment with CPLDs and hardware description language (HDL). The source files for the project are in open source KiCad format so you can modify the circuit diagram and PCB if needed."
Categories: Planet FPGA

Xilinx UltraScale SelectIO CTLE Demo includes ADS Simulations

Distributed Feeds - May 14, 2014 - 9:22am
Thanks to Romi Mayder and Ravindra Gali for including screen shots of their ADS simulations in this video demo of the continous time linear equalizer (CTLE) in the SelectIO of the UltraScale chip.
Categories: Planet FPGA

Xilinx and Agilent DDR4 at 2400 Mb/s for JEDEC Compliance

Distributed Feeds - April 18, 2014 - 6:52am

Thanks to Xilinx for this video clip featuring my colleague Ai-Lee Grumbine demonstrating our DDR4 compliance app on their demo board with the UltraScale 2400Mb/s DDR4 controller. (Please be patient: the video stream takes a few seconds to buffer.)

Categories: Planet FPGA

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