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A few weeks ago, I have been pleased to attend IECON2013 in Vienna and had the chance to meet my friend Luis Gomes from the University Nova of Lisboa, Portugal. While discussing together, he took some time to give me some details about a web-based framework that he designed with his team. This framework is called “IOPT-Tools” and this is a on-line Petri Net editor. Petri nets are useful to modelize any type of process and are used in many different applications (e.g. workflow management or UAV fault diagnostics).
What’s cool about this tool (other than being web-based, i.e. not having to install it on your desktop computer) is that once your have modelized your system, you can run all sorts of analysis to validate system behavior and even automatically generate VHDL code or C code to embed your model inside a controller. Here is a screen shot of a model used for BLDC motor commutation:
This tool in totally in line with current discussions in the EDA community regarding the migration of EDA tools in the cloud (see Cadence blog or Synopsis blog on this). EDA in the cloud in the idea of having tools for chip/embedded system design being offered as Software-As-a-Service (SaaS) and running on powerful servers so that even small teams could leverage important computing power they could not afford otherwise. With the rising complexity of chip design, it is well known that always more computing power is needed to compile designs and the solution won’t come from the standard computing solutions.
Congrats to the team of Dr. Gomes for their vision in developping this new tool ! You can access it and use it right now for FREE by following this link.
For more information regarding this tool, you can also consult some publications on the IEEE Explore. If somehow you use this tool and want to publish an article at the next IEEE IES IECON2014 conference in Dallas, TX, watch for the Call for Paper here.
The post EDA Tool in the cloud: A web-based IOPT Petri Net Editor appeared first on PE-FPGA/IP.com.
For some work developing HDMI-compatible FPGA code, I needed to observe the control signals with a scope. So I built up this little breakout PCB. The high-speed video TMDS signals are routed directly through from one connector to the other. I tried to keep them equal length and as short as possible. Don't have any way to verify impedance and reflections, but it works ok on one TV with short HDMI cables.
The low speed (CEC, SCL, etc) signals are brought out to the header in the back in the photo. Jumpers allow the signals to pass through, or they can be disconnected to test and modify them.
The PCB is shared on OshPark. See http://oshpark.com/profiles/sensicomm if you want to use this design. It uses standard HDMI female connectors, available from DigiKey and many other vendors. Soldering the fine-pitch surface mount pins on the connectors is a bit of a challenge. I tried soldering individual pins, but ended up using the flood it with solder and mop up the excess with solder-wick method.
Linear Technology: Dual 13A or Single 26A μModule Regulator Integrates Digital Power System Management
By the way, your fear is true, Quartus II compilation for Cyclone V FPGA device requires Windows 64-bit OS. I had tried to compile a few designs targeting Cyclone V FPGA using a 32-bit Windows 7 Professional laptop with 4Gbytes memory, it all ended with failure due to out of memory. In fact, one of the designs was a relatively small design with around 1800 logic elements using the smallest Cyclone V GX device 5CGXFC3BF7F23C8.
Anyway, this is not a nightmare. You just need to plan ahead by preparing yourself a PC with Windows 64-bit OS if you are serious in using any Cyclone V device in your new design.
Well, compiling a simple 32-bit counter won’t crash, though.
Are you registered for the next IECON2013 in Vienna ? It’s still time to plan your trip !
If you happen to be there, I invite you to attend the Technical Session on Electronic System-on-chip in Power Application that I will chair with Dr. Éric Monmasson. Here is the program:TT04 1 – Electronics System-on-Chip in Power Applications
Room: D – 358 / 359 , Day: Wednesday 13th of November. Hour: 08:30, Duration: 120 minutes. Chair/s: Eric Monmasson, Marc Perron.
Title: Industrial Electronic Control: FPGAs and Embedded Systems Solutions
Prof. Luis Gomes, Univ. Nova Lisboa, Portugal
Prof. Eric Monmasson, University of Cergy-Pontoise, France
Prof. Marcian Cirstea, Anglia Ruskin University, United Kingdom
Prof. Juan J. Rodriguez-Andina, Universidad Vigo, Spain
Title: Real-Time Embedded Control for Point-On-Wave Switching
Dr. Anton Poeltl, Abb, USA
Title: Medium Voltage 6-pulse Current Source Rectifier with a Novel Shunt Active Power Filter Connection
Dr. Mostafa Hamad, Arab academy for science and technology, Egypt
Dr. Mahmoud Masoud, Sultan Qaboos University, Oman
Dr. Khaled Ahmed, University of Aberdeen, United Kingdom
Prof. Barry Williams, University of Strathclyde, United Kingdom
Title: Rapid Prototyping Framework for Real-Time Control of Power Electronic Converters Using Simulink
Mr. Bruno dos Santos, Faculty of Engineering, University of Porto, Portugal
Prof. Rui Esteves Araújo, Faculty of Engineering, University of Porto, Portugal
Mr. Diogo Varajão, Faculty of Engineering, University of Porto, Portugal
Mr. Cláudio Pinto, Faculty of Engineering, University of Porto, Portugal
Title: Comparative of HLS and HDL Implementations of a Grid Synchronization Algorithm.
Mr. Fco. Manuel Sánchez, Alcalá University, Spain
Dr. Raúl Mateos, Alcalá University, Spain
Dr. Emilio J. Bueno, Alcalá University, Spain
Mr. Javier Mingo, Alcalá University, Spain
Mrs. Inés Sanz, Alcalá University, Spain
Title: Sliding Mode Direct Power Control of three-phase PWM boost rectifier using a single DC current sensor
Ms. Marwa Ben Said-Romdhane, Enit, Tunisia
Dr. Mohamed Wissem Naouar, Enit, Tunisia
Prof. Ilhem Slama-Belkhodja, Enit, Tunisia
Prof. Eric Monmasson, Université de Cergy Pontoise, Tunisia
If you plan to be there and want us to meet, just send me a note ! See you there !
The post IECON2013: Electronics System-on-Chip in Power Applications appeared first on PE-FPGA/IP.com.
The name might sound complicated enough, but the project is actually a fun to use synthesizer –sequencer which also has an added ability to sample and compose. This project was built by two people as their final year project for Cornell University. As far as the hardware part is concerned, they use an Altera DE2 FPGA board for processing the data and a popular software by Mathworks named MATLAB as a user interface since it has an ability to create interactive GUI without much input.
The synthesizer uses a combination of sampled and additively synthesized sounds to produce various instruments. The FPGA based sequencer takes input from a MATLAB GUI and sequences each instrument separately, allowing the user to make compositions in real-time. Moreover, an automatic gain control algorithm was designed and implemented to ensure that overflow would not result in distorted output. The design starts with user input to a screen of buttons on a MATLAB GUI. These sequences are periodically pushed out through a National Instruments Analog-Digital Converter into the GPIO port of the Altera DE2 board which is read by the Altera board and is processed according to the sample received.
Yaaay! Another FPGA project from Cornell guys! These guys used the DE2 FPGA board to pursue solving the problem of generating color NTSC signals and wanted to show that the VGA DAC (Digital to Analog Converter) is able to handle it.
Sounds simple? How about if I tell you that the DE2 FPGA Boards don’t have NTSC ports built into them? NTSC output without NTSC ports – our friends from Cornell got us covered, get the freakin VGA port spit out NTSC signals and not just one but two!
General Purpose color NTSC generators were used, NTSC signals are pushed out the VGA pins at full frame rate in 315×242 pixel resolution. Thats the video part so who takes care of the battleship game logic – A NIOS II system runs the battleship code and takes care of the input coming from the two players, the score keeping and feeding location to the NTSC signal generators.
Earlier this year we ran an extensive tour of our High-speed Digital Design and Verification Seminar in over twenty European cities (see map below). We were joined by an impressive list of partner presenters including Xilinx, Micron, TE Connectivity (formerly Tyco Electronics), Thales, and many others. The feedback we recieved was very positive so we’ve posted all the papers at the link above. The titles are:
- Agilent’s Presentations
- Welcome and Introduction: Reminder “Design to Prototyping” season 1 & objectives of 2013 seminars
- Advanced 3D EM analysis for Pre- and Post- Layout PCB design and verification: Anticipate Signal Integrity issue on your High Speed Digital links
- Explore your design space including IBIS AMI models with Advanced Channel Simulation and Optimization for early evaluation of design trade-offs
- How to characterize and debug high speed digital links on your physical prototype – what part of your design is eating up your Eye margins? – Part 1
- How to characterize and debug high speed digital links on your physical prototype – what part of your design is eating up your Eye margins? – Part 2
- Partner’s Presentations:
- Xilinx: The Do’s and Don’ts of High Speed Serial Design in FPGAs
- MathWorks: Developing Customised Measurements and Automated Analysis Routines using MATLAB®
- Micron: DDR2, DDR3 and DDR4 DRAM, highlighting specific features, performance characteristics and design guidelines that are essential to your design and test decisions
- TE Connectivity: High-speed connector model validation through EM extraction and correlation with measurements
- Thales: An Innovative Simulation Workflow for Debugging High-Speed Digital Designs using Jitter Separation
- D&P Electronic System: Channel Analysis of a High Speed Digital Module and Correlation between Simulation and Measurement
We hope the papers will have value to you in your work.
2013-05-24 I have written a blog about the Microprocessor (R)evolution published at All Programmable Planet.
2013-01-08 My article "Four soft-core processors for embedded systems" is published in EE Times.
2012-12-21 My "FPGA design from scratch" blog is the top one programmable logic design article in EE Times in 2012.
2012-06-20 I have written a blog about MicroBlaze at All Programmable Planet.
2012-06-01 Here is my first post at All Programmable Planet.
2012-05-24 After all these years I am now a professional blogger at All Programmable Planet.
2012-05-08 Read about my new blog in EE Times.