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FPGA Central Blogs - July 29, 2015 - 11:00pm
Categories: Planet FPGA

Open Source FPGA Toolchain Builds CPU

Distributed Feeds - July 28, 2015 - 8:31am

When you develop software, you need some kind of toolchain. For example, to develop for an ARM processor, you need a suitable C compiler, a linker, a library, and a programmer. FPGAs use a similar set of tools. However, instead of converting source code to machine language, these tools map the intent of your source code into configuration of FPGA elements and the connections between them.

There’s some variation, but the basic flow in an FPGA build is to use a synthesizer to convert Verilog or VHDL to a physical design. Then a mapper maps that design to the physical elements available on a particular FPGA. Finally, a place and route step determines how to put those elements in a way that they can be interconnected. The final step is to generate a bitstream the chip understands and somehow loading it to the chip (usually via JTAG or by programming a chip or an external EEPROM).

One problem with making your own tools is that the manufacturers typically hold the bitstream format and other essential details close to their chest. Of course, anything can be reverse engineered (with difficulty) and [James Bowman] was able to build a minimal CPU using  an open source Lattice toolchain. The project relies on several open source projects, including  IceStorm, which provides configuration tools for Lattice iCE40 FPGAs (there is a very inexpensive development platform available for this device).

We’ve covered IceStorm before. The IceStorm project provides three tools: one to produce the chip’s binary format from an ASCII representation (and the reverse conversion), a programmer for the iCEstick and HX8K development boards, and database that tells other open source tools about the device.

Those tools blend with other open source tools to form a complete toolchain–a great example of open source collaboration. Yosys does the synthesis (one of the tools available on the EDAPlayground site). The place and route is done by Arachne. The combined tools are now sufficient to build the J1A CPU and can even run a simple version of Forth. If you’ve ever wanted to play with an FPGA-based CPU design, you now have a $22 hardware option and free tools.

Categories: Planet FPGA

Altera’s Stratix 10 is a marvel of high-performance FPGA design

Distributed Feeds - July 27, 2015 - 11:45pm

Together with Xilinx, Altera has been the other half of the two-party system driving the FPGA arms race forward for many years. Big headlines were made when it was recently announced that Intel would would buy Altera in a $6.7 billion cash deal. Among other things, Intel will be acquiring Altera’s new Stratix 10 chip, a device some are calling “the most significant step forward in high-end FPGAs.”

The chip features the revolutionary HyperFlex core fabric architecture built on the Intel 14 nm Tri-Gate process. This equates to a 2X core performance gain over other high-performance FPGAs at up to 70% lower power. The Hyperflex design addresses some of the issues that come in to play at high GHz frequencies. The primary concern is minimizing the so-called propagation delay — the time it takes a signal to travel from one register to the next. There are two components to propagation delay, the logic or gate delay, and the routing or wiring delay.

Normally, one might try to speed things up by widening the buses to move more things in parallel. The downside is that a much larger die is generally needed, and it also consumes more power. Instead, Altera focussed on the routing delay by simply adding more registers. The key is that their ‘hyper-registers’ can be associated not only with each routing segment on the chip, but also with the other amenities like DSP and embedded memory. Unlike general registers, hyper-registers also include the option to be bypassed.

On the design end — not the chip design itself, but rather the design that the user burns into the chip — this bypassing feature allows optimal register location to be automatically programmed in after the ‘place-and-route’ step. The place-and-route is typically what the designer does after creating the circuit (the set of logic elements together with the netlist connecting them), by popping the logic and connections into their desired places and pins on the chip.

Some other features that caught our eye include the integrated quad-core 64 bit 1.5 GHz ARM Cortex-A53 hard processor system, and 10 TFLOPS of IEEE 754 compliant single precision floating point DSP. The heterogeneous 3D System-in-Package (SiP) integration also sounds cool, although I am not really sure what all that entails. It must be good, because with up to 5.5 million logic elements the chip claims itself to be the highest density highest density FPGA fabric available.

Clearly not business analysts, we have nonetheless noted that only a few companies have so far availed themselves of Intel’s 14nm process, with Altera being one of the majors. Apparently, Intel has indicated they will be integrating FPGAs into future Xeon products to add some processor customization capability. Gaining access to Altera’s technology at a deeper level should definitely complement the FPGA packaging services that Intel already provides for customers.

40.712784 -74.005941
Categories: Planet FPGA

Running LEON3 on ZedBoard Tutorial

Distributed Feeds - July 25, 2015 - 4:36am

LEON3? FPGA? ?? ??? soft-core processor ? ? ???, SPARC V8 ????? ???? ??[1]. ?? ??? Cobham Gaisler?? ???? ???, ??/?? ???? ??? ??? ? ?? (GNU GPL ????). RTL? ?? ???? ????? ? ? ????? LEON3? ????. LEON3? ??? ZedBoard? ????, ? ?? ???? ?????. ? ???? ZedBoard? LEON3? ???, ???? ???? ?? ???? ??? ????? ??.

??? XUPV5-LX110T(ML509) ??? OpenSPARC? ???? ??? ????. OpenSPARC? Sun?? ??? ???? ??????[6,7]. OpenSPARC? XUPV5-LX110T? ??? ?? ?? ???? ???[8]. ?? ?? ??? ?? ?????. 10?? ?? ??? ????? ??????, ??? ???? ?? ??? ????? ???. ?? ??? ?? ???? ?? ???, ?? ???? ??? ?? ??? ???. ?? ?? ?? ?? ??? ?? ????? ??. ???? ?? ??? ???????, ISE 10.1 ?? ??? ???? ??? ??? ???. ? ?? ????? ???? ??? ???? ???. ??? Xilinx?? ???? ? ? ???, ???? ?? ?? ??? ???? (VCS, Vera, Debussy). ?? ?? ?? ??? ??? ?? ?? ????.

?? ?? LEON3? ????? ? ???? ???, ???? ??? ?? (??? ???). ?? ??? ??? ???? ?? ??? ? ???. ?????? Realtime Embedded?? ???? ????? ??? ???[10]. LEON3, OpenRISC 1200, Nios2, MicroBlaze ?? ????? ??. LEON3? ?? ??? ???, ???? ?? ?? ????. Realtime Embedded? ?? ??? ? ???? ???, ??? ?? ???? ?? (?? ??), ?? ??? ???? ?, ?? ??? ???? ??? ZedBoard? ?? ????? ??? ?? ???.

1. ZedBoard ??
2. ?? ?? ??
– 1) grlib ???? ? ??
– 2) Xilinx Vivado 2013.4 ??
– 3) ??? ?? ?? ? Digilent ???? ??
3. LEON3 ?? ? ZedBoard? ???
– 1) grlib ?? ?? ??
– 2) LEON3 ??
– 3) ZedBoard? leon3mp.bit ???
4. grmon? ??? LEON3 ?? ? ??? ??
– 1) grmon ??
– 2) grmon? ??? LEON3? ??
– 3) ??? ??? ???? ? ??
5. ??? ??? ?? ? ??
– 1) ?? ? ???? ? ??
– 2) buildroot
– 3) leon linux ??
– 4) mklinuximg
– 5) grmon? ??? LEON3 ??, ??? ??

1. ZedBoard ??
ZedBoard? Zynq-7000 all-programmable SoC? ?? ?? ????[4, 11]. Zynq-7000? all-programmable SoC? ? ??? ????, ZedBoard? ??? ??? ? ??? ?? ??? ????. Zynq-7000? ??? ?? ??? ZedBoard ??? ZC702, ZC706 ?? ??[15]. ?? ???? ZedBoard? ??? ?? ??? LEON3? ?????. ZedBoard? ?? ?? ??? ???? ??? ??? ?? ??[16]. ???? ????? ??? ??????, LEON3? ??? ???? ????? ?? ??? ???? ??. ZedBoard ?? ?? ?? ? ?? ??? The Zynq Book[14], An FPGA Tutorial using the ZedBoard[17], ZedBoard Training and Videos[18], Zynq design from scratch[19]? ???? ??. ? ?? Xilinx Documentation? ? ???? ?? ??? ?? ??. ZedBoard? Zynq-7000? ? ??? LEON3? ??? ?? ?? ???, ? ??? ??? ?? ??? ???? ??.

2. ?? ?? ??
LEON3? ???? ZedBoard? ??? ???? grlib(LEON3 ?? ??), Vivado(?? ??), digilent ????? ???? ???? ??.

1) grlib ???? ? ??
Cobham Gaisler ????? ???, LEON3/GRLIB source code? GRFPU netlist? ??????[20].

$wget $wget $tar -xzvf grlib-gpl-1.4.1-b4156.tar.gz $cd grlib-gpl-1.4.1-b4156 $tar -xzvf ../grlib-netlists-gpl-1.4.1.tar.gz

??? ??? grlib? ???? ??? ??? ??

$cd grlib-gpl-1.4.1-b4156 $tree -L 1 ??? bin ??? boards ??? designs ??? doc ??? lib ??? Makefile ??? netlists ??? software

boards ????? ?? ??? ?? ??? ?? ???, designs ????? ?? ??? ?? ??? ?? ??. designs ?????? make ???? ??? LEON3? ????, ?? LEON3? ?? ? ??. ZedBoard? ??, ./grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702? ????. ?? ?? ? ?? ??? ?? ??? ? ???? ??? README.txt? ???? ???, ?? ???? ??.

2) Xilinx Vivado 2013.4 ??
Xilinx ????? ??? Vivado Design Suite 2013.4 ??? ??????. ??? Vivado Design Suite 2013.4 ??? ???? ??(README.txt ??). ??? ??? LEON3? ?? ? ??? ??? ?? ???.

??? ?? ?? ???, ?? ???? ??? ??? ???? ??? ??? ??.

$tar -xvf Xilinx_Vivado_SDK_2013.4_1210_1.tar $cd Xilinx_Vivado_SDK_2013.4_1210_1 $sudo ./xsetup

? ??? ?? ? ???? ?? ??? ? ??? ??? ???, Xilinx ???? ???? ???[22]. ?????? ?? ??? ?? ???? ??? ?? ??? ?? ???, ? ??? ?? ?? ? ??[16].

???, ??? ?? ???? Xilinx cable driver ?? ??? ???? ???. Ubuntu 14.04.2 Desktop, 64bit?? ? ??? ???? ???? ??? ????. Cable driver? ?? ???? ????.

3) ??? ?? ?? ? Digilent ???? ??
????? USB-UART? ????? ??? ???? ??? ???? ??. CONFIG_USB_SERIAL_CYPRESS_M8=y, CONFIG_USB_ACM=y? ??? ??? ???? ??[23]. ?? ??? ?????, ??? ??? ?? ?? ?? ?????? ?? ???? ??. ?? ?? ??? ??? ??? ? ??? ???? ???? ??[24]. ???? ????? ZedBoard? USB-UART ??? ???? ? /dev/ttyACM0 ??? ??? ? ??.

???? Digilent? ????? ????.

$wget $sudo dpkg -i digilent.adept.runtime_2.16.1-2_amd64.deb

?????? ??? ??????, ??? ?? ?? ? ??. USB-JTAG, USB-UART? ??? ????? ????? ?? 1) ZedBoard? ??? SD ??? ??? ???? ????, ?? ??? ??, 2) ??? ????? ZedBoard? ???? ??? ????? ???? ???.

??? ??? ??? ????(?) ??? ????? ?? ??.

3. LEON3 ?? ? ZedBoard? ???
???? ZedBoard ?? ??? ???? LEON3 ?? ??? ???? ???.
?? LEON3? ???? ZedBoard? ???? ? ??.

1) grlib ?? ?? ??
?? ZedBoard? ???? ????? ./grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702?? ????. ??? ?? ZedBoard? ZC702? ?? ????, ??? ZedBoard? ??? ??? ????? ??[26,27]. ./grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702/leon3mp.xdc ??? ?????? ??.

ZedBoard? ??? ??? ???? ???, ??? grmon? ??? LEON3? ??? ? ??? ?? ??? ????[28].

$./grmon -xilusb -nb -u GRMON2 LEON debug monitor v2.0.65 32-bit eval version Copyright (C) 2015 Cobham Gaisler - All rights reserved. For latest updates, go to Comments or bug-reports to [email protected] This eval version will expire on 10/12/2015 Xilusb: Cable type/rev : 0x3 JTAG chain (2): xc7x020 zynq7000_arm_dap Warning: Failed to call Tcl_Init. Some TCL functions won't be working properly To avoid this warning, see Installation section in the manual about the environment variable GRMON_SHARE AMBA plug&play not found! Failed to initialize target! Exiting GRMON

ZedBoard? ??? ./grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702/leon3mp.xdc? ?? ?????? ??.

?? ?? ?? ??

#set_property PACKAGE_PIN T22 [get_ports {led[0]}] set_property PACKAGE_PIN P17 [get_ports {led[7]}] set_property PACKAGE_PIN P18 [get_ports {led[6]}] set_property PACKAGE_PIN W10 [get_ports {led[5]}] set_property PACKAGE_PIN V7 [get_ports {led[4]}] set_property PACKAGE_PIN W5 [get_ports {led[3]}] set_property PACKAGE_PIN W17 [get_ports {led[2]}] set_property PACKAGE_PIN D15 [get_ports {led[1]}] set_property PACKAGE_PIN E15 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS18 [get_ports {led[6]}] set_property IOSTANDARD LVCMOS18 [get_ports {led[5]}] set_property IOSTANDARD LVCMOS18 [get_ports {led[4]}] set_property IOSTANDARD LVCMOS18 [get_ports {led[3]}] set_property IOSTANDARD LVCMOS18 [get_ports {led[2]}] set_property IOSTANDARD LVCMOS18 [get_ports {led[1]}] set_property IOSTANDARD LVCMOS18 [get_ports {led[0]}] #LEFT btn set_property PACKAGE_PIN G19 [get_ports {button[0]}] #RIGHT btn set_property PACKAGE_PIN F19 [get_ports {button[1]}] set_property PACKAGE_PIN J18 [get_ports {button[2]}] set_property PACKAGE_PIN K18 [get_ports {button[3]}] set_property PACKAGE_PIN N19 [get_ports {switch[0]}] set_property PACKAGE_PIN N20 [get_ports {switch[1]}] set_property PACKAGE_PIN N17 [get_ports {switch[2]}] set_property PACKAGE_PIN N18 [get_ports {switch[3]}] set_property PACKAGE_PIN M15 [get_ports {switch[4]}] set_property PACKAGE_PIN M16 [get_ports {switch[5]}] set_property PACKAGE_PIN P16 [get_ports {switch[6]}] set_property PACKAGE_PIN R16 [get_ports {switch[7]}] #create_clock -name clk100 -period 10.0 [get_ports gclk] set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks clk_fpga_1] set_false_path -from [get_clocks clk_fpga_1] -to [get_clocks clk_fpga_0]

?? ?? ?? ??

set_property IOSTANDARD LVCMOS33 [get_ports led] set_property PACKAGE_PIN T22 [get_ports {led[0]}] set_property PACKAGE_PIN T21 [get_ports {led[1]}] set_property PACKAGE_PIN U22 [get_ports {led[2]}] set_property PACKAGE_PIN U21 [get_ports {led[3]}] set_property PACKAGE_PIN V22 [get_ports {led[4]}] set_property PACKAGE_PIN W22 [get_ports {led[5]}] set_property PACKAGE_PIN U19 [get_ports {led[6]}] set_property PACKAGE_PIN U14 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS18 [get_ports switch] set_property PACKAGE_PIN F22 [get_ports {switch[0]}] set_property PACKAGE_PIN G22 [get_ports {switch[1]}] set_property PACKAGE_PIN H22 [get_ports {switch[2]}] set_property PACKAGE_PIN F21 [get_ports {switch[3]}] set_property PACKAGE_PIN H19 [get_ports {switch[4]}] set_property PACKAGE_PIN H18 [get_ports {switch[5]}] set_property PACKAGE_PIN H17 [get_ports {switch[6]}] set_property PACKAGE_PIN M15 [get_ports {switch[7]}] set_property IOSTANDARD LVCMOS18 [get_ports button] set_property PACKAGE_PIN R16 [get_ports {button[0]}] set_property PACKAGE_PIN N15 [get_ports {button[1]}] set_property PACKAGE_PIN R18 [get_ports {button[2]}] set_property PACKAGE_PIN T18 [get_ports {button[3]}] set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks clk_fpga_1] set_false_path -from [get_clocks clk_fpga_1] -to [get_clocks clk_fpga_0]

2) LEON3 ??
./grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702 ?????? make ???? ??? LEON3? ??? ? ??. LEON3? ??? ???? ./grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702/leon3mp.bit ??? ??? ? ??.

?? Makefile? ???? ??? ?????.
make help ???? ?? ??? ??? ??? ? ??.
?? ??? ????? ?? ?? ?? ???? ??? LEON3? ????.
XUPV5-LX110T(ML509)? ???? make ise?, ZedBoard? ?? make vivado? ????.

$cd ./grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702 $make help interactive targets: make alint-launch : start alint elaboration time linting make avhdl-launch : start active-hdl gui mode make riviera-launch : start riviera make vsim-launch : start modelsim make ncsim-launch : compile design using ncsim make actel-launch : start Actel Designer for current project make ise-launch : start ISE project navigator for XST project make ise-launch-synp : start ISE project navigator for synplify project make quartus-launch : start Quartus for current project make quartus-launch-synp : start Quartus for synplify project make synplify-launch : start synplify make vivado-launch : start Vivado project navigator make planahead-launch : start PlanAhead project navigator make xgrlib : start grlib GUI batch targets: make alint-comp : alint compilation time linting make avhdl : compile design using active-hdl gui mode make vsimsa : compile design using active-hdl batch mode make riviera : compile design using riviera make vsim : compile design using modelsim make ncsim : compile design using ncsim make ghdl : compile design using GHDL make actel : synthesize with synplify, place&route Actel Designer make ise : synthesize and place&route with Xilinx ISE make ise-map : synthesize design using Xilinx XST make ise-prec : synthesize with precision, place&route with Xilinx ISE make ise-synp : synthesize with synplify, place&route with Xilinx ISE make isp-synp : synthesize with synplify, place&route with ISPLever make quartus : synthesize and place&route using Quartus make quartus-map : synthesize design using Quartus make quartus-synp : synthesize with synplify, place&route with Quartus make precision : synthesize design using precision make synplify : synthesize design using synplify make vivado : synthesize and place&route with Xilinx Vivado make planahead : synthesize and place&route with Xilinx PlanAhead make dc : synthesize design usign Synopsys Design Compiler make fm : Formal equivalence check using Synopsys Formality make scripts : generate compile scripts only make clean : remove all temporary files except scripts make distclean : remove all temporary files

make vivado ??? ??? LEON3? ????.

$cd ./grlib-gpl-1.4.1-b4156/designs/leon3-xilinx-zc702 $make vivado

3) ZedBoard? leon3mp.bit ???
?? ?? ?? leon3mp.bit ??? ZedBoard? ??? ??.
make program-zc702 ???? ??? leon3mp.bit? ZedBoard? ???.

$make program-zc702 xmd Xilinx Microprocessor Debugger (XMD) Engine Xilinx EDK 2013.4 Build EDK_2013.4.20131205 Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. XMD% Programming Bitstream -- ./vivado/leon3-zc702/leon3-zc702.runs/impl_1/leon3mp.bit Fpga Programming Progress ............10.........20.........30.........40.........50.........60.........70.........80.........90........Done Successfully downloaded bit file. JTAG chain configuration -------------------------------------------------- Device ID Code IR Length Part Name 1 4ba00477 4 Cortex-A9 2 23727093 6 XC7Z020 JTAG chain configuration -------------------------------------------------- Device ID Code IR Length Part Name 1 4ba00477 4 Cortex-A9 2 23727093 6 XC7Z020 -------------------------------------------------- Enabling extended memory access checks for Zynq. Writes to reserved memory are not permitted and reads return 0. To disable this feature, run "debugconfig -memory_access_check disable". -------------------------------------------------- CortexA9 Processor Configuration ------------------------------------- Version.............................0x00000003 User ID.............................0x00000000 No of PC Breakpoints................6 No of Addr/Data Watchpoints.........4 Connected to "arm" target. id = 64 Starting GDB server for "arm" target (id = 64) at TCP port no 1234 Note:: init_user command is Deprecated. Use ps7_post_config from ps7_init.tcl

?????? ???? ??? ?? ?? ???.


4. grmon? ??? LEON3 ?? ? ??? ??
?? LEON3? ??? ???? ??? ???, ? ? ??? ?? grmon??. grmon? ??? ??? ???, LEON3? ??? LEON3? ??? ????? ??? ???? ??? ??? ? ??. grmon ?? Cobham Gaisler?? ????.

1) grmon ??

$wget $tar -xzvf grmon-eval-2.0.65.tar.gz $export GRMON_SHARE=/path/to/grmon/linux/share

Cobham Gaisler?? ???? grmon? 32bit? ?????? 64bit Ubuntu?? ? ???? ?? ? ??. ?????? ?? ??? ?? ??? ??? ? ???, ?? ??? ???? ??? (??? ??? ???? ??). 32bit? ?????? ??? ??? ?? ???? ??? ? ???. ???? ???? ???? ?? ??? ? ?? ?? ???[29].

2) grmon? ??? LEON3? ??
??? ??? grmon? ??? LEON3? ??? ? ??.

$cd ./grmon-eval-2.0.65/linux/bin $./grmon -xilusb -nb -u

? ?? ??? ??, ???? grmon? Xilinx? USB-JTAG? ???? ???? ???. USB-JTAG? ???? ???? ?? ???. ??? ??? parallel JTAB cable? ???? ??.

3) ??? ??? ???? ? ??
?? ???? ??? ?? LEON3? ??? ????? ???? ??, ?? ???? ?? ??? ???? ?????. ?? ???? ?? ??? ???? ????, grmon? ??? ????.

$wget $./grmon -xilusb -nb -u GRMON2 LEON debug monitor v2.0.65 32-bit eval version Copyright (C) 2015 Cobham Gaisler - All rights reserved. For latest updates, go to Comments or bug-reports to [email protected] This eval version will expire on 10/12/2015 Xilusb: Cable type/rev : 0x3 JTAG chain (2): xc7x020 zynq7000_arm_dap GRLIB build version: 4156 Detected frequency: 83 MHz Component Vendor LEON3 SPARC V8 Processor Cobham Gaisler JTAG Debug Link Cobham Gaisler Generic AHB ROM Cobham Gaisler AHB/APB Bridge Cobham Gaisler LEON3 Debug Support Unit Cobham Gaisler Xilinx MIG DDR2 Controller Cobham Gaisler Generic UART Cobham Gaisler Multi-processor Interrupt Ctrl. Cobham Gaisler Modular Timer Unit Cobham Gaisler General Purpose I/O port Cobham Gaisler AHB Status Register Cobham Gaisler Use command 'info sys' to print a detailed report of attached cores grmon2> load /path/to/image.dsu 40000000 .stage2 10.0kB / 10.0kB [===============>] 100% 40004000 .vmlinux 3.1MB / 3.1MB [===============>] 100% Total size: 3.10MB (1.53Mbit/s) Entry point 0x40000000 Image /tmp/image.dsu loaded grmon2> run Booting Linux Booting Linux... PROMLIB: Sun Boot Prom Version 0 Revision 0 ... Execution Finished, Exiting Please press Enter to activate this console. Sash command shell (version 1.1.1) />ls bin dev etc home init lib mnt proc sbin sys tmp usr var />

??? ?? ??? ?? ??? ? ??.

5. ??? ??? ?? ? ??
???? ??? ???? ?? ??? ??? ?? ????.

1) ?? ? ???? ? ??
??? ???? ???? ???? ? ??? ????. sparc-linux-ct-multilib-0.0.7, leon-buildroot-2013.02-1.0.3, leon-linux-3.10-3.10.58-1.0.4, mklinuximg-2.0.9? ????. sparc-linux-ct-multilib-0.0.7? SPARC? ????? ???? ?????, buildroot? LEON3? ??? ?? ???? ?????. leon-linux? ?? ???? ??? ?? ???? ?????, mklinuximg? ??? LEON3? ?? ? ?? ?? ???? ??? ? ??.

$wget $wget $wget $wget $tar -xvf sparc-linux-ct-multilib-0.0.7.tar.bz2 $tar -xvf leon-buildroot-2013.02-1.0.3.tar.bz2 $tar -xvf leon-linux-3.10-3.10.58-1.0.4.tar.bz2 $tar -xvf mklinuximg-2.0.9.tar.bz2 $export PATH=$PATH:/path/to/sparc-linux-4.4.2-toolchains/multilib/bin

2) buildroot
?? make install ???? ????.

$cd /path/to/leon-buildroot-2013.02-1.0.3 $make install

???? make build ???? ???, buildroot configuration? ????.

$make build

??? ?? buildroot? ????.

Target Architecture: SPARC Target Architecture Variant: v8 Toolchain - Toolchain path (New): /path/to/sparc-linux-4.4.2-toolchains/multilib Filesystem images - cpio the root filesystem: yes

????? Save an Alternate Configuration File? ??? ??? ????. make build ???? ?? ???? ???? ./buildroot-git/output?? ??? ??? ??? ? ??.

$make build $ls ./buildroot-git/output rootfs.cpio rootfs.tar

3) leon linux ??
???? leon linux? ????. leon-linux-3.10-3.10.58-1.0.4.tar.bz2 ???? ??? ??? ????, ?? ????? ??.

$cd /path/to/leon-linux-3.10-3.10.58-1.0.4/ $git clone git://

LEON3?? ???? ??? ? ??? ??? ?? ??? ????.

$cd linux $git checkout v3.10 $patch -p1 < ../patches/0001-sparc32-leon-older-LEON3-4-designs-need-explicit-dat.patch $patch -p1 < ../patches/0002-sparc32-leon-prevent-long-uart-fifo-discovery-loop.patch $patch -p1 < ../patches/0003-Avoid-using-UART-during-PHY-initialization.patch $patch -p1 < ../patches/0004-spi-add-support-for-aeroflex-gaisler-spimctrl.patch $patch -p1 < ../patches/0005-apbuart-add-polling-callbacks-to-apbuart-driver.patch $patch -p1 < ../patches/0006-apbuart-add-support-for-virtual-KGDB-GRMON-channel.patch $patch -p1 < ../patches/0007-xsysace-Add-support-for-LEON-GRLIB-SoCs.patch $patch -p1 < ../patches/0008-usb-gadget-Add-UDC-driver-for-Aeroflex-Gaisler-GRUSB.patch $patch -p1 < ../patches/0009-greth-moved-TX-ring-cleaning-to-NAPI-rx-poll-func.patch $patch -p1 < ../patches/0010-sparc32-dma_alloc_coherent-must-honour-gfp-flags.patch $patch -p1 < ../patches/0011-sparc-Let-memset-return-the-address-argument.patch $patch -p1 < ../patches/0012-sparc-leon-Fix-race-condition-between-leon_cycles_of.patch $patch -p1 < ../patches/0013-sparc32-leon-Make-leon_dma_ops-available-when-CONFIG.patch $patch -p1 < ../patches/0014-sparc32-Implement-xchg-and-atomic_xchg-using-ATOMIC_.patch $patch -p1 < ../patches/0015-sparc32-leon-Align-ccall_info-to-prevent-unaligned-t.patch $patch -p1 < ../patches/0016-sparc32-destroy_context-and-switch_mm-needs-to-disab.patch $patch -p1 < ../patches/0017-sparc-optimize-MMU-fault-trap-entry.patch $patch -p1 < ../patches/0018-sparc-leon-workaround-for-MMU-errata.patch $patch -p1 < ../patches/0019-sparc-leon-Distinguish-between-IRQMP-and-IRQAMP-inte.patch

??? ?? ??? linux ?? ?? ???? ??? ????.

$cd .. $pwd /path/to/leon-linux-3.10-3.10.58-1.0.4 $cp config/config_up linux/.config

?? ??? ?? ???? ??? ??? ???.

$cp /path/to/leon-buildroot-2013.02-1.0.3/buildroot-git/output/rootfs.cpio /path/to/leon-linux-3.10-3.10.58-1.0.4/../dist/.rootfs.cpio

????? make ???? ??? ??? ???? ????.

$make build LINUX_TREE=linux

4) mklinuximg
????? mklinuximg? ??? LEON3? ?? ? ?? ???? ????.

$cd /path/to/mklinuximg-2.0.9 $./mklinuximg /path/to/leon-linux-3.10-3.10.58-1.0.4/linux/arch/sparc/boot/image image.dsu

? ???? ?? ?? ?? ??? ?? ??? ?????, ??? ?? ???? ??. ??? ?? ??? ???? ????? ??? ????, ?? ???? ??. (/path/to/mklinuximg-2.0.9/src/prom.c)

5) grmon? ??? LEON3 ??, ??? ??

$cd /path/to/grmon $./grmon -xilusb -nb -u grmon2> load /path/to/image.dsu 40000000 .text 4.2kB / 4.2kB [===============>] 100% 400010F0 .data 80B [===============>] 100% 40004000 .vmlinux 7.2MB / 7.2MB [===============>] 100% 4072B0C0 .startup_prom 39.6kB / 39.6kB [===============>] 100% Total size: 7.20MB (1.52Mbit/s) Entry point 0x40000000 Image /path/to/image.dsu loaded grmon2> run ... Welcome to Buildroot buildroot login: root #

[1] LEON3 Processor,
[2] Soft microprocessor, Wikipedia,
[3] Cobham Gaisler,
[4] ZedBoard,
[5] Xilinx University Program XUPV5-LX110T Development System, Xilinx,
[6] OpenSPARC Overview, Oracle,
[7] OpenSPARC, Wikipedia,
[8] ???, 20150721,
[9] LEON SPARC Mailing List,
[10] CoreX, Realtime Embedded,
[11] ZedBoard Zynq-7000 Development Board, Digilent,,400,1028&Prod=ZEDBOARD&CFID=13708886&CFTOKEN=bf9bf59caa35919f-A2243CAC-5056-0201-026AF17F0DA09716
[12] Zynq-7000 All Programmable SoC, Xilinx,
[13] What is ZYNQ? (Lesson 1), Microelectronic Systems Design Research Group,
[14] The Zynq Book,
[15] Zynq-7000 Boards, Kits, and Modules, Xilinx,
[16] ???, ZedBoard ?? ?? ?? ? ??? ??,
[17] Pete Johnson, An FPGA Tutorial using the ZedBoard,
[18] Training and Videos, ZedBoard,
[19] Sven Andersson, Zynq design from scratch. Part 1.,
[20] Download LEON/GRLIB, Cobham Gaisler,
[21] Downloads, Xilinx,
[22] Xilinx Design Tools: Installation and Licensing Guide, Xilinx,
[23] Cypress-USB2UART-Ver1.0G driver for Linux?, ZedBoard,
[24] ???, Kernel Compile and Multi-booting using Grub2,
[25] Digilent Adept, Digilent,
[26] leon3 with grmon on Xilinx zc702,
[27] Differences between ZedBoard and Xilinx Zynq-7000 SoC ZC702 Evaluation Kit, ZedBaord,
[28] GRMON Cannot Start,
[29] ???,

Categories: Planet FPGA

Altera (ALTR) update (July 23)

Distributed Feeds - July 23, 2015 - 7:30am
ALTERA shares will likely test support @ $46.71 (2011 high). Waiting for this level to enter this ma
Categories: Planet FPGA

Hackaday Prize Entry: An FPGA'd Propeller

Distributed Feeds - July 21, 2015 - 10:00pm

The Parallax Propeller is an exceptionally interesting chip that doesn’t get the love it deserves. It’s a 32-bit microcontroller with eight independent cores that are each powerful enough to do some real computation.  Around this time last year, the source for the Propeller was opened up and released under GPL 3.0, along with the mask ROM and an interpreter for the Propeller-specific language, Spin. This release is not only a great educational opportunity, but a marvelous occasion to build some really cool hardware as [antti.lukats] is doing with the Soft Propeller.

[antti]’s Soft Propeller is based on the Xilinx ZYNQ-7000, a System on Chip that combines a dual core ARM Cortex A9 with an FPGA with enough logic gates to become a Propeller. The board also has 16MB of Flash used for configuration and everything fits on a Propeller-compatible DIP 40 pinout. If you’ve ever wanted to play around with FPGAs and high-power ARM devices, this is the project for you.

[antti] already has the Propeller Verilog running on his board, and with just a bit more than 50% of the LUTs used, it might even be possible to fit the upcoming Propeller 2 on this chip. This build is just one small part of a much larger and more ambitious project: [antti] is working on a similar device with HDMI, USB, a MicroSD, and 32MB of DDR2 RAM. This will also be stuffed into a DIP40 format, making it an incredibly powerful system that’s just a bit larger than a stick of gum.

The 2015 Hackaday Prize is sponsored by:
Categories: Planet FPGA

Learn FPGAs in your Browser

Distributed Feeds - July 21, 2015 - 1:01am

FPGAs aren’t really programmed, they are configured. Most designers use Verilog or VHDL to describe the desired circuit configuration. Developers typically simulate these configurations before committing them to silicon (a good habit, especially if you ever graduate from FPGAs to ASICs where changes are very expensive). That simulation takes a lot of software you have to install and learn, right?

Not necessarily. You can do e-mail, word processing, and PCB layout in your browser. Why not FPGA design? The EDAPlayground website provides two editor views: one for your main “code” and another for the testbench (the simulation driver you use to test your design). You can even open multiple files, if you have a complex design.

Once you’ve entered your Verilog or VHDL (or picked one of many examples) you can run the simulation and see the result right in your browser. No software to install, and–outside of actually learning VHDL or Verilog–not much learning curve.

As [Strauburn], [combinatorylogic], and others commented on our recent post about a VHDL CPU, you can do a lot of learning without ever having your hands on real hardware. The web site gives you access to several different tools (useful if you want to see how your code will behave on different tools) and also many standard verification libraries. There are limited synthesis tools, but honestly, if you want to go to real hardware, you are going to want the vendor tools for the specific FPGA you are using.

As for learning the actual art of FPGA development, a quick search for Verilog tutorial or VHDL tutorial on the web or YouTube will get you started. Verilog is very C-like and VHDL is more like Ada, so choose accordingly. If you are craving VHDL, you can’t go wrong with Free Range Factory’s free book. For Verilog, this list will get you started.

Categories: Planet FPGA

Designing a CPU in VHDL for FPGAs: OMG.

Distributed Feeds - July 20, 2015 - 10:00am

If you’ve been thinking about playing around with FPGAs and/or are interested in CPU design, [Domipheus] has started a blog post series that you should check out. Normally we’d wait until the whole series is done to post about it, but it’s looking so good, that we thought we’d share it with you while it’s still in progress. So far, there are five parts.

minispartan6In Part One, [Domipheus] goes through his rationale and plans for the CPU. If you’re at all interested in following along, this post is a must-read. The summary, though, is that he’s aiming to make a stripped-down 16-bit processor on a Spartan 6+ FPGA with basic arithmetic and control flow, and write an assembler for it.

In Part Two, [Domipheus] goes over the nitty-gritty of getting VHDL code rendered and uploaded to the FPGA, and as an example builds up the CPU’s eight registers. If you’re new to FPGAs, pay special attention to the test bench code at the end of the post. Xilinx’s ISE package makes building a test suite for your FPGA code pretty easy, and given the eventual complexity of the system, it’s a great idea to have tests set up for each stage. Testing will be a recurring theme throughout the rest of the posts.

In Part Three, [Domipheus] works through his choices for the instruction set and starts writes up the instruction set decoder. In Part Four, we get to see an ALU and the jump commands are implemented. Part Five builds up a bare-bones control unit and connects the decoder, ALU, and registers together to do some math and count up.


We can’t wait for further installments. If you’re interested in this sort of thing, and are following [Domipheus]’s progress, be sure to let him know: we gotta keep him working.

Of course, this isn’t the first time anyone’s built a soft-CPU in an FPGA. (The OMG was added mostly to go along with the other TLAs.) Here’s a tiny one, a big one, and a bizarre one.

Categories: Planet FPGA

Why Intel Should Make a Challenging and Daring Bid for Micron

Distributed Feeds - July 17, 2015 - 9:15am

RAMMicron Technology Inc. (NASDAQ: MU) has had a solid week, with its shares bouncing handily on the heels of a reported $23 billion buyout offer from China’s Tsinghua Unigroup. There is just one problem, and that is not just that it may be a low-ball buyout offer. This proposed deal either will or should be blocked by U.S. regulators.

24/7 Wall St. has a thought here that should seriously be considered, and it comes with an up-front admission that the odds of success would seem to be very low. Intel Corp. (NASDAQ: INTC) should make a matching bid for Micron, with a promise of matching any such bid by Tsinghua Unigroup. Admittedly, U.S. and international regulatory bodies almost certainly would be all over Intel, trying to block this effort. That being said, there have not yet been enough loud voices against a proposed Chinese chip-making giant buying Micron.

Another complication comes up as well here. Intel has a working collaboration with Tsinghua Unigroup. Intel even invested roughly $1.5 billion for what was reported as a 20% stake in Tsinghua Unigroup. Intel may worry that reaching for Micron could harm its relationship with the Chinese outfit. Again, a merger of this magnitude is larger than mere share prices.

What is at stake here in a proposed acquisition of Micron by China is not just an issue of national pride. It is an issue of national security. Micron is U.S.-based and has much of its operations and many of its more than 30,000 employees here inside the United States. It claims to have the broadest memory solutions portfolio in the semiconductor industry, and it says that it holds over 20,000 patents. Micron makes critical DRAM and flash memory that is used in electronics, personal computers, internal systems and just about everything short of a basic toaster or wind-up alarm clock. That involves military, defense, law enforcement, government, corporate and consumer electronics alike.

ALSO READ: 10 Stocks to Own for the Next Decade

This proposal also would have an implication for Altera Corp. (NASDAQ: ALTR). Intel is trying to acquire this programmable logic devices-maker for $54 per share in a deal valued at some $16.7 billion. If the deal goes through, then Altera will become a unit of Intel, targeting existing and new customer sales. Intel signaled that it will continue Altera’s support and development of ARM-based and power management products.

As of July, Intel did not seem to have an assured regulatory clearance in its effort to acquire Altera. The company said that it expected a period of six to nine months to close the deal, and that was more than six weeks ago. If Altera is being acquired for $54, then the current price of $50.30 indicates that there is at least some regulatory risk to the deal closing.

Back to regulatory deal risk: The desire for Tsinghua Unigroup to buy up Micron almost has to be challenged by U.S. regulators. The Chinese would not allow a U.S. technology giant to come into China and buy up one of its top technology players. The Chinese might block a deal like that out of pride or security, and they have laws about what foreign companies can really own in China.

Tsinghua Unigroup is a Chinese company that is part of what is considered to be China’s top science university, Tsinghua University. To make an easy reference, let’s just call this the MIT-equivalent of China. And let’s not overlook the notion that China owns and controls state assets and entities. In late 2013, Tsinghua Unigroup made two acquisitions, of Spreadtrum and of RDA Microelectronics. Those were even larger than its market cap, so where did the funds come from? It is no secret at all that China wants to have its own dominant technology sector.

ALSO READ: AMD and Intel Are 2 Very Different Companies

Effectively, this would lead to a mostly state-run Chinese chipmaker taking over the top U.S. memory maker. The take of 24/7 Wall St. is that, despite nearly certain regulatory efforts immediately rallying against it, it would be better to have a U.S. monopoly of Intel-Micron (or even Intel-Micron-Altera) than it would be to have a state-owned Chinese chipmaker holding all our chips.

The Committee on Foreign Investment in the United States (CFIUS), the chair of which is the Secretary of the U.S. Treasury, reviews transactions that could result in control of a U.S. business by a foreign person or entity to determine the effect of such transactions on the national security of the United States. Again, think of all the flash memory and DRAM that is inside of national security equipment, on top of everything else.

Now let’s consider another issue here. Jack Lew, Treasury Secretary, just met with the Chinese delegation in Washington for the seventh meeting of the Strategic and Economic Dialogue, which is targeted at strengthening bilateral economic cooperation between the United States and China. Was this acquisition offer for Micron brought up? Did China get a nod? Did China get told to back off? Or did China point out how much Treasury debt it holds?

Needless to say, a Chinese company effectively owning the last chipmaker of DRAM and flash that is truly a U.S. operation should be considered something in which there are huge national security risks. CFIUS has a mixed history here, but if you consider that chips are used in nearly every single piece of defense and security equipment in the United States and abroad, then Micron’s ownership and domicile should matter. Still, a report in Forbes indicated that the proposed acquisition from China could be approved.

ALSO READ: Cisco’s Daring $10 Billion Investment in China

While some may have real concerns, there is no assurance that CFIUS would attempt to block the deal. It allowed IBM to sell its PC business to Lenovo, but it blocked the Chinese from buying 3Com. Still, Hewlett-Packard recently announced the sale of a majority stake in its Chinese server, storage and technology assets for $2.3 billion to Tsinghua University (Tsinghua Holdings) to become H3C. Bloomberg said at the time that was the first major U.S. technology company to pass control to local owners since the government stepped up restrictions on foreign firms.

If Intel owned Micron it would be one massive powerhouse, even far more than it already is. The antitrust concerns would be massive if Intel was able to control every aspect of the chip and memory sector. Still, if you only had two choices, would you rather have a Chinese state-run outfit owning a prized asset like Micron or would you rather let a U.S. giant keep all of Micron’s technology, most of its employees and its intellectual property (more than 20,000 patents) in America?

In 2013 Micron acquired Elpida, which also has ties to China, despite being based in Japan. Micron’s announcement in February of 2013 said that the Chinese Ministry of Commerce gave antitrust clearance for Micron’s pending acquisition of Elpida. Here is what stood out the most: China’s approval was the last remaining antitrust pre-merger clearance required for completion of the transaction.

This question over whether Micron should go to China or stay put does not even address the price of the proposed buyout. The $23 billion implied purchase price would be at $21.00 per share. This also would be a crushing deal for many Micron shareholders, and it would be a low-ball buyout, if history and analyst values matter at all.

ALSO READ: The 6 Most Shorted Nasdaq Stocks

Trading at $19.60 or so, Micron has a 52-week range of $17.14 to $36.59, and its consensus analyst price target is $29.64. That means the average of all analysts covering Micron, even after they largely lowered their targets, value Micron at almost $30 per share.

For those Americans who may be concerned that China would own or control a critical company like Micron, CFIUS can be contacted by email at [email protected] or by phone at (202) 622-1860.

Categories: Planet FPGA

ECE5760 Robot Navigation Using Sound Localization

Distributed Feeds - July 16, 2015 - 6:03pm
"The main idea behind this project was to construct a system on the Altera DE2 board that is capable of detecting the location of a sound source. We envisioned many purposes for such an instrument in gaming and other types of systems; however, to demonstrate our sound localizing capability in this project, we decided to use it for robot control."
Categories: Planet FPGA

Fiscal Year 2011 - 2014 - Earnings Per Share Basic - Semiconductor &amp; Related Devices - SIC 3674

Distributed Feeds - July 13, 2015 - 6:03am
Earnings Per Share Basic Ticker Symbol Company Name FY 2011 FY 2012 FY 2013 FY 2014 adi ANALOG DEVICES INC $2.90 $2.18 $2.19 $2.39 altr ALTERA CORP $2.39 $1.74 $1.37 $1.53 amat APPLIED MATERIALS INC /DE $1.46 $0.09 $0.21 $0.88 amd ADVANCED MICRO DEVICES INC $0.68 $-1.60 $-0.11 $-0.53 amkr AMKOR TECHNOLOGY INC $0.48 $0.26 $0.58 $0.56 aosl ALPHA & OMEGA SEMICONDUCTOR Ltd $1.61 $0.52 $-0.22 $-0.13 atml ATMEL CORP $0.69 $0.07 $-0.05 $0.08 avgo Avago Technologies LTD $2.25 $2.30 $2.23 $1.05 brcm BROADCOM CORP $1.72 $1.29 $0.74 $1.11 cree CREE INC $1.35 $0.39 $0.75 $1.03 cy CYPRESS SEMICONDUCTOR CORP /DE/ $1.02 $-0.16 $-0.32 $0.11 emkr EMCORE CORP $-1.54 $-1.66 $0.19 $0.16 entr ENTROPIC COMMUNICATIONS INC $0.31 $0.05 $-0.73 $-1.09 fnsr FINISAR CORP $1.10 $0.47 $-0.06 $1.16 fsl Freescale Semiconductor Ltd. $-1.82 $-0.41 $-0.81 $0.84 fslr FIRST SOLAR INC. $-0.46 $-1.11 $3.77 $3.97 idti INTEGRATED DEVICE TECHNOLOGY INC $0.45 $0.41 $-0.14 $0.59 intc INTEL CORP $2.46 $2.20 $1.94 $2.39 ipgp IPG PHOTONICS CORP $2.87 $3.02 $3.85 irf INTERNATIONAL RECTIFIER CORP /DE/ $2.35 $-0.79 $-1.28 $0.83 issi INTEGRATED SILICON SOLUTION INC $2.11 $-0.10 $0.62 $0.77 klic KULICKE & SOFFA INDUSTRIES INC $1.77 $2.17 $0.79 $0.82 kopn KOPIN CORP $0.05 $-0.29 $-0.08 $-0.45 lltc LINEAR TECHNOLOGY CORP /CA/ $2.52 $1.71 $1.72 – lscc LATTICE SEMICONDUCTOR CORP $0.66 $-0.25 $0.19 $0.41 mchp MICROCHIP TECHNOLOGY INC $2.24 $1.76 $0.65 $1.99 mcrl MICREL INC $0.55 $0.21 $0.31 $0.24 mrvc MRV COMMUNICATIONS INC $-0.87 $0.72 $-0.91 – mscc MICROSEMI CORP $0.66 $-0.35 $0.49 $0.25 mu MICRON TECHNOLOGY INC $0.17 $-1.04 $1.16 $2.87 mxim MAXIM INTEGRATED PRODUCTS INC $1.65 $1.32 $1.56 $1.25 mxl MAXLINEAR INC $-0.68 $-0.40 $-0.37 $-0.19 nvda NVIDIA CORP $0.44 $0.96 $0.91 $0.75 onnn ON SEMICONDUCTOR CORP $0.03 $-0.20 $0.34 $0.43 powi POWER INTEGRATIONS INC $1.20 $-1.20 $1.95 $1.99 psmi PEREGRINE SEMICONDUCTOR CORP $-3.57 $0.19 $-0.13 – pxlw PIXELWORKS INC $-0.40 $-0.31 – – quik QUICKLOGIC CORPORATION $-0.21 $-0.29 $-0.27 $-0.23 rfmd RF MICRO DEVICES INC $0.46 $- $-0.19 $0.18 rmbs RAMBUS INC – $-1.21 $-0.30 $0.23 semi SunEdison Semiconductor Ltd – $2.92 $-1.39 $-2.17 smtc SEMTECH CORP $1.16 $1.37 $0.64 $-2.44 spir SPIRE Corp $-0.18 $-0.22 $-0.92 – spwr SUNPOWER CORP $-6.28 $-3.01 $0.79 $1.91 spwra SUNPOWER CORP $-6.28 $-3.01 $0.79 – sune SUNEDISON INC. $-6.68 $-0.76 $-2.46 $-4.40 swks SKYWORKS SOLUTIONS INC. – $1.09 $1.48 $2.44 tqnt TRIQUINT SEMICONDUCTOR INC $0.29 $-0.16 $-0.24 – tsra TESSERA TECHNOLOGIES INC $-0.38 $-0.58 $-3.48 $3.23 txn TEXAS INSTRUMENTS INC $1.91 $1.53 $1.94 $2.61 xlnx XILINX INC $2.43 $2.01 $1.86 $2.37
Categories: Planet FPGA


Distributed Feeds - July 11, 2015 - 8:03am

Just sitting with a glass of red and sorting out final bug of VHDL for Altera Lab Digital Logic part II port for the Master 21EDA board.  Looking like the multiplexers are not passing through signals for some dang blasted reason.  Will sort and post full details as soon as it is cracked.

Categories: Planet FPGA

3 Chip Stocks That Could Be the Next Sector Victims

Distributed Feeds - July 8, 2015 - 7:10am

micro chipThe overall carnage and woe in the chip sector in the first quarter is spreading to the second quarter, and the casualties are starting to add up. Micron Technology was absolutely blasted when it missed, and the AMD warning knocked the stock down at one point Tuesday almost 20%.

A new report from the SunTrust Robinson Humphrey team notes that while the personal computer issues are pretty well figured in, their work indicates that further demand drag in wireless infrastructure and what they call the “broad-based” industrial markets are factoring into weakness. They even think it could spread to the automotive sectors usage, which has been very strong over the past couple of years.

The SunTrust team focused on three specific stocks could have negative price reactions ala Micron, and they also could see downward earnings revisions. Combined with the fact that the companies have not really sold off big and have higher price-to-earnings multiples than some stocks, they could face a swift reaction when they report if the data is negative.

Analog Devices

This stock has had a big run and just recently started to roll over. Analog Devices Inc. (NASDAQ: ADI) designs, manufactures and markets analog, mixed-signal and digital signal processing integrated circuits (ICs) for use in industrial, automotive, consumer and communication markets worldwide. It offers signal processing products that convert, condition and process real-world phenomena, such as temperature, pressure, sound, light, speed and motion into electrical signals.

ALSO READ: 4 Jefferies Top Value Stocks to Buy Now

The company may have been awarded a nice a product slot in the next iPhone, according to some reports, but those revenues may not be reported anytime soon, and Apple has been known to award and then pull big design awards. Overall, Analog Devices has a bright future, the near term is what investors may need to be wary of. The company is expected to report earnings in August.

Analog Devices investors are paid a 2.57% dividend. SunTrust has the stock rated at Neutral, with a $68 price target. The Thomson/First call consensus price target is $67.32. Shares closed Tuesday at $63.38.

Maxim Integrated Products

This company supplies some chips to Samsung for the Galaxy S6. Maxim Integrated Products Inc. (NASDAQ: MXIM) designs, develops, manufactures and markets various linear and mixed-signal ICs worldwide. The company also provides a range of high-frequency process technologies and capabilities for use in custom designs. It primarily serves automotive, communications and data center, computing, consumer and industrial markets.

The stock jumped in May when chatter about a buyout from Avago started to hit the tape. Avago ultimately bought Broadcom in a massive $37 billion deal that should cool that speculation at least for the near term. While Maxim’s current business seems steady, an earnings miss and revisions talked down could take a toll in the near term. The company is expected to report on July 23.

ALSO READ: 4 Top Merrill Lynch Internet Picks for the Second Half of 2015

Maxim shareholders are paid a 3.36% dividend. SunTrust rates the stock Neural, with a $33 price target. The consensus is posted at $35.80. Shares closed Tuesday at $33.72.


This is another company that has had a nice run and looks to have rolled over on the chart. Xilinx Inc. (NASDAQ: XLNX) designs and develops programmable devices and associated technologies worldwide. Its programmable devices include ICs in the form of programmable logic devices (PLDs), such as programmable system on chips and three-dimensional ICs; software design tools to program the PLDs; targeted reference designs; printed circuit boards; and intellectual property (IP), which consists of Xilinx and various third-party verification and IP cores.

Again, with a solid portfolio of products, and the distinct possibility of it being considered as a takeover candidate, what the SunTrust team views is on a very short-term basis. That means second-quarter results, which are scheduled to be reported on July 22.

Xilinx shareholders are paid a 2.87% dividend. The SunTrust team rates the stock Neutral with a $44 price target. The consensus target is at $45.04. The shares closed most recently at $43.62.

ALSO READ: Deutsche Bank’s 3 Top Networking Stocks to Buy Now

Again, these are three top-notch companies, and the play for those that own them and want to keep them would be to hedge by either selling short against the box or putting on a costless collar. That would require selling the calls, and taking the proceeds to buy the puts on the stocks. Now if the market takes a huge swift downturn, everything will get sold, these included.

Categories: Planet FPGA

SSD1306 VHDL FPGA Implementation

Distributed Feeds - July 7, 2015 - 4:30pm

I’ve been reading up as much VHDL as possible these last few days as I’ve recently found out that the majority of my summer is going to consist of writing it! After seeing loads of implementations for HD44780 16×2 character based LCDs, I couldn’t find any examples for the easy to get LCDs (by easy, I of course mean off eBay), SSD1306 based OLEDs, Nokia 5110 PCD8544 LCDs etc…

So, instead of cursing to myself why none exist, I decided to jump right in and get it done myself! The design process itself is quite simple when split into separate blocks and the first block I wrote was the SPI block because this was the easiest. SPI as I’ve mentioned before is a brilliant protocol consisting of a clock, a data out and data in line (named MISO and MOSI – Master In Slave Out, Master Out Slave In, in the industry), along with a chip select line. In my version, I have an SPI peripheral declared as a master, with a permanently low CS (a variable in the code selects whether CS toggles after every byte). The SPI peripheral I designed allows for CPHA and CPOL to be changed (though I’ve not really tested the other modes), along with a variable size data width and clock prescaler. A word of warning: The prescaler is an integer between 0 and 7. The actual amount of prescaling is equal to 2^(Presc+1) so if the prescaler is set to 1, the SPI clock out will be 4x slower than the master clock (or thereabouts). This allows for correct clocking of slower devices. The SPI peripheral has a parallel data load bus, along with a BUSY output signal and TRIG (trigger) input signal. On the falling edge of the TRIG signal, the parallel data is loaded into the shift register and the BUSY output is set high. Once the BUSY output goes high, the host can set the TRIG low again. Upon completion of the data shifting, the BUSY output goes low and the host controller should detect this falling edge and know the SPI peripheral is now free for more data transmission. As this application is only half duplex, the SPI MISO and parallel data out ports aren’t used.

The second block is the actual LCD controller. This block sends the correct SPI commands, along with reading the internal ROM and sending the graphic data to the LCD. This block controls the SPI peripheral and initializes the LCD before sending the graphic data, along with controlling the CD line on the LCD. This is where most of the magic happens!

The final block is the ROM itself. As I have an Altera FPGA, I’ll be using a single port RAM block. I’ve also designed the system using the block diagram method within Quartus and my simulations are done using the university vector waveform method.

Testing the SPI module
SPI driven LCDs generally support not having to use the CS pin during data transmission, allowing a continuous stream of data into the LCD without the host having to worry about toggling the chip select pin as theoretically, the chips already selected! For certain devices however, where the SPI input is merely a shift register without a data counter, the CS pin is needed to latch the data and indicate the end of a transmission.

Running a prescaler of 2, along with CS toggling being disabled.

The same prescaler however, CS is set after the transfer is complete.

The fastest prescaler. Four clock cycles are required per SPI clock cycle giving a maximum clock speed of 12.5MHz with a 50MHz system clock.

Zoomed out view of the above.

Obviously, it can be seen above that the SPI interface is working. on the falling edge of the TRG input (trigger), the SPI transaction is initiated and data is shifted out as expected. During this, the BSY (busy) line is set high, indicating an SPI transaction is currently happening.

Adding in the LCD controller
The LCD controller sends data and controls the SPI peripheral through the BSY and TRIG lines. Inside the LCD controller is an array containing all the instructions required to initialize the LCD, along with the code required to interface the internal ROM and write the pixel data to the LCD. The image (as ever!) was dithered and scaled in Matlab, the bits packed and written into a .MIF file (all within Matlab actually…), which can be ready directly by the Altera compiler. The image is of my landscape test scene as ever and from far away, looks… acceptable!

QSim2_Shifting out data
Attaching the LCD controller and shifting data out! As CPHA = CPOL = 0, the clock idles low and the data is valid on the rising edge.

As can be seen in the image above, the first command is 0xA8, shifted out of the SPI peripheral, as controlled by the LCD controller, wahoo!

For simulation purposes, the clock has been increased and the prescaler decreased. The initialization phase and graphics data write phases can easily be seen by the CD transition.

And just to prove it works…

Displaying my dithered test landscape scene on an SSD1306 OLED display!

I’m not cheating! It really is connected to my FPGA.

Thankfully, my FPGA development board features an easily interfaced IDC connector socket.

I’ve got the whole project up on Github for those who want to pick through my poor commentless VHDL…

Categories: Planet FPGA

Hackaday Prize Entry: They Make FPGAs That Small?

Distributed Feeds - July 3, 2015 - 10:00pm

There are a few development boards entered in this year’s Hackaday Prize, and most of them cover well-tread ground with their own unique spin. There are not many FPGA dev boards entered. Whether this is because programmable logic is somehow still a dark art for solder jockeys or because the commercial offerings are ‘good enough’ is a matter of contention. [antti lukats] is doing something that no FPGA manufacturer would do, and he’s very good at it. Meet DIPSY, the FPGA that fits in the same space as an 8-pin DIP.

FPGAs are usually stuffed into huge packages – an FPGA with 100 or more pins is very common. [antti] found the world’s smallest FPGA. It’s just 1.4 x 1.4mm on a wafer-scale 16-pin BGA package. The biggest problem [antti] is going to have with this project is finding a board and assembly house that will be able to help him.

The iCE40 UltraLite isn’t a complex FPGA; there are just 1280 logic cells and 7kByte of RAM in this tiny square of programmable logic. That’s still enough for a lot of interesting stuff, and putting this into a convenient package is very interesting. The BOM for this project comes out under $5, making it ideal for experiments in programmable logic and education.

A $5 FPGA is great news, and this board might even work with the recent open source toolchain for iCE40 FPGAs. That would be amazing for anyone wanting to dip their toes into the world of programmable logic.

The 2015 Hackaday Prize is sponsored by:
Categories: Planet FPGA

Breakout board for the DAC900E a 165 MSPS @ 10 Bit DAC

Distributed Feeds - June 27, 2015 - 10:21am

This breakout board helps me to interface my FPGA with the DAC900E from Texas Instruments.
The DAC has 165 MSPS and 10 bits which is quite some speed.
The combination FPGA and DAC opens up for experiments with digital signal processing, like making a direct digital synthesizer (DDS), digital modulation and many more. The DAC is fast enough to use it in the TX part for a shortwave radio without any analog mixer required.

A detailed description can be found:

Categories: Planet FPGA

Really, Really Retro Computer On An FPGA

Distributed Feeds - June 23, 2015 - 1:00am

[Daniel Bailey] built himself a scaled-down clone of a very early computer in an FPGA. Specifically, he wrote some VHDL code to describe the machine in question, a scaled-down clone of the Manchester Small-Scale Experimental Machine with an 8-bit processor and a whopping 8 bytes of RAM, all of which are displayed on an LED screen. Too cool.

That he can get it to do anything at all with such constraints amazes us. Watch him program it and put it through its paces in the video below the break.

The coolest thing about the original “Manchester Baby” is that it retains memory in a Williams tube, which is essentially a CRT with an electrical pickup plate covering up the screen. You know how you get a static charge on the face of an old CRT where the electron beam hit? Well, it turns out that you can read this electric field for a while, and use it as a short-term memory element.

The builders of the SSEM included a second CRT screen so that you could visualize the entire 32×32 bits of memory on a screen, like you would. Naturally, [Daniel] had to replicate this feature on his Manchester Baby clone, but with an 8×8 LED matrix. Now we want one of those for our laptop.

The VHDL is up on Github, as is a Javascript simulator of the machine. And if you’re interested, there’s an active retro-computing Google+ group where this and similar projects are bantied about. And check out some of the earliest computer music, made on a descendant of the Manchester Baby.

Thanks [Ed] for the tip.

Categories: Planet FPGA

Altera Cyclone IV FPGA Graphics controller Part 2: 160x120 resolution increase!

Distributed Feeds - June 17, 2015 - 9:44am

After managing to get my graphics controller working at a mediocre resolution of 100×75, I wanted to squeeze as much performance out of this chip as possible! Unfortunately, due to memory constraints, this meant rewriting the VGA controller to work at a different resolution. The original controller was running at a resolution of 800×600, which when divided by 8 gives us the 100×75 pixel resolution with each 100×75 macropixel consisting of 8x 800×600 pixels. I’m using power of two resolution divisions as this allows me to calculate the memory addresses through only two shifts and a multiply, as opposed to 2 shifts and 3 multiplies (along with much more logic space…). Therefore, the next logical size up will be 4x sized macropixels, meaning a total resolution of 200×150. All seemed great after I changed the memory widths and hit compile. Disaster! Turns out, my FPGA only contains 30x M9K memory blocks whereas for a resolution of 200×150 (at 8bpp), would’ve required 32x M9K blocks! I can’t help but feel a little gutted that only two M9K blocks were holding me back from the prime resolution of 200×150 pixels.

I then reattached my thinking hat and thought of other methods of squeezing out the best performance I could from this chip. If 200×150 was the next step from 100×75 for a master resolution of 800×600, why not change to a different master resolution and subdivide that? And so that is what I did. I’ve now rewritten the VGA controller to work at 640×480 though I need to test how temperamental it is in the long term. Since my master clock is 48MHz, the best I can achieve with the PLL is a pixel clock of either 25.2MHz (supposed to be 25.175MHz) or 31.5MHz. Of these two, the 25.175MHz clock is the industry standard, however since I can actually properly synthesize the 31.5MHz clock, I’ll be using this. This will give a refresh rate of either 73Hz in VGA mode of 75Hz in VESA mode.

Now that I’m running my monitor at 640×480, I can group the pixels into 4×4 macropixels (640×480/4 = 160×120) while also storing the whole framebuffer in my onboard dual port SRAM! This is pretty much the best resolution that I can achieve in my setup without the use of external RAM though even this small increase in resolution (1.6:1.33..), video playback has reduced to a sloooooow 6.6fps.

Oh yeh, it turns out I had a small error in my original block diagram file where the memory clock is meant to be the same as the shift register clock. This was causing erratic pixel errors at high write rates.Quar2
Rerouting the memory clock

Using the same test pic of me and Kim, the quality is much better than with the previous 100×75 version.

Nothing like a close up, still got those random cyan artifacts on our noses…

Testing the display with my landscape test image

…And a closeup! The macropixels being smaller really adds to increased quality.

Keep tuned for more updates!

Categories: Planet FPGA

Altera Cyclone IV Graphics Controller + STM32F0 MCU = 100x75 video!

Distributed Feeds - June 16, 2015 - 8:09pm

Well, this week so far has been very productive with regards to electronics! This is a project I’ve been wanted to do for ages just haven’t got round to doing. I’ve previously designed VGA controllers on both my CPLD and my FPGA board but I’ve not actually done anything useful other than design a bouncing box and display a few colour bars so I finally thought: why not actually try developing a full graphics controller, how hard can it be?!

The answer to that is actually “not very hard”, I managed to get it working relatively well in one evening of coding, displaying text, images and (unsynchronised) video!

While I love my STM32F0, and wouldn’t swap it for any other platform, it is limited when it comes to precision timing events (or more so, I’m limited in my assembly knowledge!) so all I’m essentially doing is outsourcing all of the precision timing events to the FPGA and shifting data to the FPGA from my STM32F0.

The FPGA side of things is essentially just a super dumb half duplex unidirectional memory interface. The FPGA expects a 24bit SPI transfer consisting of the memory address and pixel data.

Block diagram file for the FPGA VGA Controller

Yes, I know that the block diagram method of Altera is for lazy people but I am lazy and don’t see the point in port mapping (for this application) when everything is so much easier to visualise in the block diagram format! Regardless, each section has a different use and I’ll go through what those uses are.

“SR” (Inst4, bottom left):

This is the main interface to the world! Its pretty much a 24bit SIPO shift register where it accepts 24bits in serial form and outputs 24 bits in parallel form (to the busses PDO and MADDR), along with controlling the WR input of the dual port SRAM. To ensure the system is kept stable, the incoming clock, data and latch inputs are synchronised to the the c1 clock, running at 192MHz. The reason this clock is so fast is to ensure the FPGA can capture every edge of the SPI clock/latch from the STM32F0. I’m clocking the STM32F0 SPI at 24MHz and without a drastic amount of oversampling, data from the STM32F0 to the FPGA was getting corrupted.

Upon the latch input going from high to low (falling edge), the WR pin is set low and the two outputs PDO and MADDR are both set to zero. The system then clocks in 24 bits on the rising edge of the clock input (from the STM32F0). If more than 24 bits are clocked in, like a FIFO, all the original bits will get shifted out of the top and will be lost. On the next rising edge of the latch input (low to high), the WR pin is set high, along with the shifted data being written to the two output ports, PDO (Port data output) and MADDR (Memory address). On the next rising  edge of c1, this data will be written to the dual port SRAM

PLL (Inst8, farthest left):

This block does pretty much what it says in the name, it PLLs! For those who don’t know, PLLs are effective methods of creating fractional multiples of an input square wave, such as clocks, variable duty cycle pulse waves or phase shifted square waves. The reason I’m using a PLL is to provide two system clocks. One for the VGA controller and memory interface and the other for the shift register. The two output clocks, c0 and c1 have output frequencies of 48MHz and 144MHz, respectively.

VGA Controller (Inst, top right):

This is where all the timing magic happens! This block generated the VSync, HSync, and colour output signals, along with the memory address of the current pixel. The memory address is generated from the horizontal and vertical counters. The actual timings used, give a resolution of 800×600 pixels which if you divide both by 8, gives the chosen resolution of 100×75, nifty huh! Fortunately, division by 8 is as simple as shifting down by 3 bits by using the srl keyword. The VGA controller section actually outputs a  16bit word per pixel as this is what the DACs on my FPGA board support. My controller however only has an 8bit video interface (256 colours). To essentially “upscale” from 8bit colour to 16bit colour, some of the most significant bits are assigned to the lower bits, on the red channel for example:

Red(4 downto 2) <= MemDI(2 downto 0);
Red(1 downto 0) <= MemDI(2 downto 1);

Where MemDI is the data into the controller from the memory module. This upscaling allows the controller to display full red, green and blue, as opposed to only displaying the top few bits. The controller also ensures that the colour outputs are zero during synchronisation phases (required for some monitors).

The VGA controller outputs a memory address to one side of the dual port SRAM and reads the data from the same side on the next clock edge, displaying it pixel by pixel to the screen.

Dual port SRAM memory (Inst7, bottom right):

Dual port SRAM is by far the easiest method of allowing both read and write operations at the same time giving a layer of separation between the shift register interface and the VGA controller. This drastically simplifies potential synchronisation problems that may become present when trying to read and write a single port SRAM at the same time. The problem here however comes with larger occupied space and increased complexity in manufacture. Fortunately for me, the FPGA I’m using (Altera Cyclone IV EP4CE6E22C8) features onboard memory blocks, allowing me to store the whole frame buffer for a 100×75, 8bit pixel screen on the FPGA. If more memory was available, I would be able to store the whole 800×600 pixel frame buffer but the amount of space increases dramatically with increasing screen sizes! I need 7,500 bytes to store a 100×75 8 bit frame buffer whereas I need 480,000 bytes to store a 800×600 8bit frame buffer! In the future, I might replace this for an SDRAM interface for my onboard SDRAM, allowing me to store the full frame buffer.

As the interface is so simple, I can shift data from the STM32F0 to the FPGA pretty fast. As the STM32F0 series features a variable length SPI interface, I can send a pixel over in two 11bit SPI writes (8 bits for the pixel colour and 13bits for the address). I have however made the shift register 24bits long, for systems that don’t support a variable length SPI interface, instead requiring 3x 8bit SPI writes. As it doesn’t take that long for the STM32F0 to send a pixel over, it actually allows relatively complex tasks such as video playback to be realisable at a relatively good frame rate. Reading  my proprietary video format off a bog standard SD card, through the SPI protocol on the STM32F0 gave an unsynchronised frame rate of ~17fps. By proprietary video format, I merely mean packing every pixel, one after another into a data file and streaming that off the SD card and into the graphics controller. No decoding/decompression takes place on the STM32F0.

The video conversion is done in Matlab where the scaling factors for the original video to the 100×75 pixel screen are first calculated, the video is then scaled and converted to RGB332 format (SLOW SLOW SLOWWWWWW) and finally written to the output data file. This process is unbelievably slow, most probably because Matlab isn’t really meant to be used for relatively heavy video processing. I’ve been meaning to get around to creating a C/C++ program to do my video processing needs but haven’t got round to it just yet… This same process is used for displaying images on the screen. The image is first scaled, then packed into RGB332 format and stored in a data file, to then be read on my STM32F0 and each pixel pushed into the screen buffer. One very fortunate thing however is the fact that as the screen is interfaced with a single function: WritePix(X, Y, Col), my previously written “GFXC” library can be used to write data to the screen! This allows me to do things like write text, draw circles, ellipses, squares and so on.

Displaying a test image of mine, a colourful “landscape” image I got off google!

That same image, up close. You can now see every macropixel.

A picture of me and my girlfriend! It looks better from afar…

…Then you see the close up and we look like we’ve been cross-stitched! I don’t know why there are random green artifacts chilling in the image.

Using my GFXC library to write some text to the screen. Believe it or not, thats the smallest font…

One of the cooler things, displaying the colour dependent mandlebrot set! Who doesn’t love good ol’ fractals.

I will at some point in the future be uploading code for this project but I wouldn’t as of yet consider it complete enough to release to the general public as there are still a few niggles that I need to iron out. Until then, keep tuned for more updates!

Oh and also, here is a quick vlog demonstrating the video playback capabilities:

Categories: Planet FPGA

Any Replacement For Altera EPCQ Devices?

Distributed Feeds - June 16, 2015 - 1:09am
I previously wrote an article “Any Replacement For Altera EPCS Devices?” in year 2006.  I hope it has helped a lot of engineers out there.  This article serves the same purpose.  I just want to raise the same awareness here especially if this is your very first time using Altera FPGAs.  You can confidently replace the expensive EPCQ devices with N25Q serial flash from Micron.  The price difference is really huge!  Look at price table below.  I don’t even need to elaborate more.  Prices are quotated from Digikey or Newarkwebsite as of today. Density Altera Part Number Price (USD$) Micron Part Number Price (USD$) 32Mb EPCQ32SI8N 11.00 N25Q032A13ESC40G 1.08 64Mb EPCQ64SI16N 18.00 N25Q064A13ESE40E 1.64 128Mb EPCQ128SI16N 30.00 N25Q128A13ESE40E 1.88 256Mb EPCQ256SI16N 50.00 N25Q256A13ESF40G 3.06
Besides the cost difference, there is a huge advantage by using N25Q128 or N25Q064.  Their packages are both SOIC-8 whereas EPCQ64 and EPCQ128 are only available in SOIC-16 packages as of today.  This could save you some board space!
I personally had tested N25Q128A13ESE40E and N25Q256A13EF840E on hardware to configure Altera FPGAs in both Active Serial x4 and Active Serial x1 modes.  It works fine.  No issue for the Quartus II software programmer to program the POF files into these N25Q devices, too.
Categories: Planet FPGA

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