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Hi all:
is negative in VHDL free of overflow?
like this
signal din : std_logic_vector(7 downto 0);
.....
when i do
cout <= std_logic_vector(- signed(din));
for example when din equal b"10000000" in complient binary = -128,
after negate it, we got 128 : b"10000000" , is it a overflow? how to
get the right answer? what is the best way to do

Hi!
Can I do this:
if (flag = '1') then
flag <= '0';
....
Thanks!

as there is readmemh in verilog to read a file and put it into
memory... is there any relevant thing in VHDL which can do this.

[link]

Hi,
What is the default value for the last_event attribute? For example
what will be s'last_event when previously no action performed on "s"?
In modelsim it seems it is a very big value.

I've had some curious symptoms with a big pile of code (not all mine) that I'd appreciate the community's inputs regarding (if it's frustrated me, it's probably frustrated the rest of you at some time).
I'm having problems getting consistent behavior in a Modelsim test bench (it did work at some time, but now it seems to generally fail). When I fix it to work in the test bench, then it bombs in synthesis (Modelsim 5.8d, Synplify Pro 8.8.x).

Hi All
Im using ncvhdl version 6.11. For some reason, the uniform function
suddenly does not work as required. The seed value does not change on
different calls to the uniform function. I have debugged my program to
find out the error but have not been successful. So, I have to write a
random generator function (that need not be synthesized). Could

Hi,
I'm new to testbenches so I set a goal to get some examples
to work under ModelSim PE Student Edition 6.4.
I'm trying to do the simplest of things - to simulate a vhdl file.
However once compiled, I have no objects hence nothing that can be added
to the waveform.
I get no errors at all, just no objects after I compile. I see the file

Following is the code... Though in the process "process_count", I have
the signal "count" in the sensitivity list, reset1 is not going to '0'
after the desired count value as is given below in the code. What is
the problem? I am using modelsim.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

Hi,
Is it possible to get back the ".vhd" file which is annotated with
delay values coming from the SDF file?
Now:
...
q_OBUF_D2 : X_AND2
port map (
I0 => a,
I1 => b,
O => q );
...
After that
...
q_OBUF_D2 : X_AND2
generic map (
tipd_I0 => (10.000 ns, 10.000 ns),

Hi,
I'm trying to code a bit stuffing entity with serial input/output
(i.e. input="1", then output = "10", input="0", then output "00"), all
synchronized by clock. At the moment i only know the following
options:
1. Use rising and falling edge of the clock to output 2 bits (original
bit and stuff bit) in one period -> Not synthetizable

Hi,
I'm studying simulating a simple AND gate (in Xilinx). Xilinx uses
X_AND2 for this. I found that "variable O_GlitchData" is uninitialized
when calling VitalPathDelay01 routine from "timing_b" package at this
line "GlitchData.SchedTime <= NOW". Is this really uninitialized or I
missed sg.? I know Xilinx maybe uses an accelerated version of this

FPGA/CPLD Design Group on LinkedIn
Group for People Involved In the Design and Verification of FPGA's and
CPLD's to Exchange Idea's and Techniques. You should have FPGA/CPLD
Design/Verification on your Profile to Join. (The focus is more on
FPGA/CPLD in the product as opposed to FPGA's solely as a path to an

Hi,
I have loosely followed the threads on this group and tried to extract some
wisdom from everybody. This is quite useful to me /now/ because I'm
implementing a "simple" SPI master interface for my Actel board.
So I tried to use a single process idea as described by M. Treseler
and his interesting [link]

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Hi,
I am having problem using/programming this kind of Flash memory in
VHDL.
I made a simple design to test it but I could not make it run as I
wanted. To be the more accurate in my testing I have decided to test
the "Read identifier Codes" since it is a command that requires 2
cycles : the first one is a write cycle and the second one is the read

i've used the 'simple_name attribute in the following manner:
variable v_my_var : integer;
variable v_line : line;
--- lots of code
write(v_line , v_my_var'simple_name & string'(" = ") );
write(v_line , integer'image(v_my_var) );
writeline(output , v_line);
The benefit is that if the name v_may_var changes, then the write

Hi all,
I need to build an ASIC synthesizable fixed point 32x32 multiplier and
fixed point 32/32 divider with very less hardware resource for my
design.Speed is not at all a matter for me.
I can space 100s of cycles for my computaions.
Can anybody help me with the code (preferably in VHDL) or suitable

OK, so I tried the following synthesis example -
various declarations omitted to save space.
I have been able to try this on five different
synthesis tools, spanning the whole range of
cost and FPGA-vs-ASIC. The results surprised
me a little - it's a long time since I did such
a complete survey.
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