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FPGA newsgroup
comp.lang.verilog
Discussing Verilog and PLI.
Updated: 5 hours 34 min ago
Snooper Module in Verilog
Hi,
I am required to use a Snooper module to test a Memory Controller.
I basically require it to verify if the "data writes into the memory"
& "data reads from the memory" are operating without errors in
accordance with the correctness of the address & correctness of the
data.
To elaborate, I have the following scenario:
I am required to use a Snooper module to test a Memory Controller.
I basically require it to verify if the "data writes into the memory"
& "data reads from the memory" are operating without errors in
accordance with the correctness of the address & correctness of the
data.
To elaborate, I have the following scenario:
Categories: News Groups
help on a complex macro
Hi,
Can somebody explain what is m3 meant to be doing in this code?
And before that, is it a valid verilog code?
`define m1(a1,a2) a1 = a1 - a2;
`define m2(a2,a3) (a2 * a3)
`define m3(t) `" calling : `\`"m1(t)`\`"AND `\`m2(t)` \`"`"
module mod;
reg v1, v2, v3;
always begin
`m1(v1,v2);
Can somebody explain what is m3 meant to be doing in this code?
And before that, is it a valid verilog code?
`define m1(a1,a2) a1 = a1 - a2;
`define m2(a2,a3) (a2 * a3)
`define m3(t) `" calling : `\`"m1(t)`\`"AND `\`m2(t)` \`"`"
module mod;
reg v1, v2, v3;
always begin
`m1(v1,v2);
Categories: News Groups
`default net_type none
I remember seeing that the directive
`default net_type none
was defined for Verilog2001 to allow undeclared variables to not
revert to single wires but instead to flag an error such as a non-
declared variable, a misspelling, or capitalization problems.
I'm not finding this information in any of my conveniently accessible
`default net_type none
was defined for Verilog2001 to allow undeclared variables to not
revert to single wires but instead to flag an error such as a non-
declared variable, a misspelling, or capitalization problems.
I'm not finding this information in any of my conveniently accessible
Categories: News Groups
call for papers - ISQED09
Call for Papers
ISQED 2009, 10th Anniversary of International Symposium on
QUALITY ELECTRONIC DESIGN
March 16-18, 2009. DoubleTree Hotel, San Jose, CA, USA
[link]
Paper Submission Deadline: Oct. 17, 2008
Acceptance Notifications: November 24, 2008
Final Camera-Ready paper: January 2, 2009
ISQED 2009, 10th Anniversary of International Symposium on
QUALITY ELECTRONIC DESIGN
March 16-18, 2009. DoubleTree Hotel, San Jose, CA, USA
[link]
Paper Submission Deadline: Oct. 17, 2008
Acceptance Notifications: November 24, 2008
Final Camera-Ready paper: January 2, 2009
Categories: News Groups
request for beta testers -- TimingAnalyzer Program
Hi All,
The TimingAnalyzer is a program that can be used for drawing timing
diagrams and performing timing analysis. There is a free version that
anyone can use and a commercial version planned. You can download and
use it now.
I was announcing updates on this newsgroup hoping to find beta testers
The TimingAnalyzer is a program that can be used for drawing timing
diagrams and performing timing analysis. There is a free version that
anyone can use and a commercial version planned. You can download and
use it now.
I was announcing updates on this newsgroup hoping to find beta testers
Categories: News Groups
Fork-join clarification
I'm using fork-joins in my testbench and I just want to be sure that
the more succinct version is functionally identical to the long
version (shown below).
// Succinct
fork
run_test(instance_1);
run_test(instance_2);
join
// Long
fork
begin
run_test(instance_1);
end
begin
the more succinct version is functionally identical to the long
version (shown below).
// Succinct
fork
run_test(instance_1);
run_test(instance_2);
join
// Long
fork
begin
run_test(instance_1);
end
begin
Categories: News Groups
Custom Clock Signals
Hi,
I have a 50MHz clock and I'm trying to make something that uses a
clock signal at 21.48MHz.
The closest I can get the clock signal would be 20MHz with my ideas.
I'm not that crafty with Verilog yet, and am not sure of the
limitations etc. and am quite confused
about how to make custom signals to be frank.
I have a 50MHz clock and I'm trying to make something that uses a
clock signal at 21.48MHz.
The closest I can get the clock signal would be 20MHz with my ideas.
I'm not that crafty with Verilog yet, and am not sure of the
limitations etc. and am quite confused
about how to make custom signals to be frank.
Categories: News Groups
Questasim Equivalent commands for Icarus Verilog
Hi Folks,
There are commands in Icarus tool for compiling verilog files as given
below:
iverilog -c rtl\\files.txt
which compiles the verilog files to a.out file
and then finally the command vvp a.out is used to simulate and view
the waveform in waveform viewver.
If the same operation is to be done in Questasim what are the
There are commands in Icarus tool for compiling verilog files as given
below:
iverilog -c rtl\\files.txt
which compiles the verilog files to a.out file
and then finally the command vvp a.out is used to simulate and view
the waveform in waveform viewver.
If the same operation is to be done in Questasim what are the
Categories: News Groups
IEEE ISQED09 Call for Papers
Call for Papers
IEEE ISQED 2009, 10th Anniversary of International Symposium on
QUALITY ELECTRONIC DESIGN
March 16-18, 2009. DoubleTree Hotel, San Jose, CA, USA
[link]
Paper Submission Deadline: Oct. 17, 2008
Acceptance Notifications: November 24, 2008
Final Camera-Ready paper: January 2, 2009
IEEE ISQED 2009, 10th Anniversary of International Symposium on
QUALITY ELECTRONIC DESIGN
March 16-18, 2009. DoubleTree Hotel, San Jose, CA, USA
[link]
Paper Submission Deadline: Oct. 17, 2008
Acceptance Notifications: November 24, 2008
Final Camera-Ready paper: January 2, 2009
Categories: News Groups
incrementing a 1-bit register?
Hi,
I'm new to verilog and i wanted to know, what would happen if i were
to increment a 1-bit register over and over? would it just toggle
between 0 and 1? or would i produce some kind of error during
synthesis?
Thanks
I'm new to verilog and i wanted to know, what would happen if i were
to increment a 1-bit register over and over? would it just toggle
between 0 and 1? or would i produce some kind of error during
synthesis?
Thanks
Categories: News Groups
verilog adders (verilog optimization)
I had assumed Verilog would collapse constants, but I wonder if that
is
always trued/allowed?
If I have something like
reg [7:0] sig1, sig2, sig3;
always @ *
sig3 = 1 + 2 + 3 + sig1 + sig2 + 4;
There must be at least 2 adders. Is Verilog required to produce 3
adders?
The code can easily be collapsed to
is
always trued/allowed?
If I have something like
reg [7:0] sig1, sig2, sig3;
always @ *
sig3 = 1 + 2 + 3 + sig1 + sig2 + 4;
There must be at least 2 adders. Is Verilog required to produce 3
adders?
The code can easily be collapsed to
Categories: News Groups
Coding Practices for Combinational and Sequential circuits
Hi,
I have been always been taught so and try to strictly follow the
practice of splitting my design into combinational and sequential
blocks (see example below). However, I have been asked to look at
somebody's design at my workplace that does not do so, and I do not
know whether I should ignore his style or bring it to the notice of
I have been always been taught so and try to strictly follow the
practice of splitting my design into combinational and sequential
blocks (see example below). However, I have been asked to look at
somebody's design at my workplace that does not do so, and I do not
know whether I should ignore his style or bring it to the notice of
Categories: News Groups
FPGA/CPLD Design Group on LinkedIn
FPGA/CPLD Design Group on LinkedIn
FPGA/CPLD Design Group on LinkedIn
Group for People Involved In the Design and Verification of FPGA's and
CPLD's to Exchange Idea's and Techniques. You should have FPGA/CPLD
Design/Verification on your Profile to Join. (The focus is more on
FPGA/CPLD in the product as opposed to FPGA's solely as a path to an
FPGA/CPLD Design Group on LinkedIn
Group for People Involved In the Design and Verification of FPGA's and
CPLD's to Exchange Idea's and Techniques. You should have FPGA/CPLD
Design/Verification on your Profile to Join. (The focus is more on
FPGA/CPLD in the product as opposed to FPGA's solely as a path to an
Categories: News Groups
AES decrytion =>ASIC
Hey folks , i need ur opinion about something :
To implement an AES 256 decryption (CBC mode ) algorithm in ASIC ,
what
would be the best way to do it ? i mean among these architectures
which one do you choose and why :
* Basic iterative architecture
* Partial loop unrolling
* full loop unrolling
* Partia outer-round pipelining
To implement an AES 256 decryption (CBC mode ) algorithm in ASIC ,
what
would be the best way to do it ? i mean among these architectures
which one do you choose and why :
* Basic iterative architecture
* Partial loop unrolling
* full loop unrolling
* Partia outer-round pipelining
Categories: News Groups
SVA Question
I am new to SVAs. I am trying to detect when a signal is a pulse (i.e.
either asserted or de-asserted for just one clock cycle). The signal
can change state, but I want it to remain in the state for at least 2
clock cycles. I may want to change this to at least n clock cycles
once I have the asertion working correctly. Below is the construct I
either asserted or de-asserted for just one clock cycle). The signal
can change state, but I want it to remain in the state for at least 2
clock cycles. I may want to change this to at least n clock cycles
once I have the asertion working correctly. Below is the construct I
Categories: News Groups
Verilog simulation of placed/routed netlist using verilog XL
Hi,
I want to simulate the verilog netlist of placed and routed design
obtained from Cadence SoC Encounter. I have the sdf file from SoC
Encounter. I am using Verilog XL. I used the sdf_annotate command in
my testbench as follows
initial begin
$sdf_annotate("./design.sdf",i nstance_name,,,,);
I want to simulate the verilog netlist of placed and routed design
obtained from Cadence SoC Encounter. I have the sdf file from SoC
Encounter. I am using Verilog XL. I used the sdf_annotate command in
my testbench as follows
initial begin
$sdf_annotate("./design.sdf",i nstance_name,,,,);
Categories: News Groups
<OT> ModelSim Help <OT>
Hi,
I'm new to testbenches so I set a goal to get those Verilog examples
to work under ModelSim PE Student Edition 6.4.
I'm trying to do the simplest of things - to run the counter.v and
tcounter.v simulation and create a waveform. However once compiled, I
have no objects hence nothing that can be added to the waveform.
I'm new to testbenches so I set a goal to get those Verilog examples
to work under ModelSim PE Student Edition 6.4.
I'm trying to do the simplest of things - to run the counter.v and
tcounter.v simulation and create a waveform. However once compiled, I
have no objects hence nothing that can be added to the waveform.
Categories: News Groups
Asynchronous FIFO - Different widths of Input & Output Ports.
Hi,
I require to use an Asynchronous FIFO, so as to allow a safe and
synchronised data transfer across two clock domains.One was the write
domain (clk_w) at which,the data (256 bit wide) is written into the
FIFO buffer (256 bit wide and 32 depth).The data nput port to the FIFO
is 256 bit wide.Other was the read domain (clk_r), at which the data
I require to use an Asynchronous FIFO, so as to allow a safe and
synchronised data transfer across two clock domains.One was the write
domain (clk_w) at which,the data (256 bit wide) is written into the
FIFO buffer (256 bit wide and 32 depth).The data nput port to the FIFO
is 256 bit wide.Other was the read domain (clk_r), at which the data
Categories: News Groups
[PLI] cbValueChange callback behavior at time 0
Hello,
I have a question about the correct cbValueChange behavior for a
callback at simulation time 0.
I use the $my_monitor system task from the Sutherland PLI handbook. The
system task is called at simulation time 0 in the following way:
addbit i1 (a, b, ci, sum, co);
initial
$my_monitor(i1);
I have a question about the correct cbValueChange behavior for a
callback at simulation time 0.
I use the $my_monitor system task from the Sutherland PLI handbook. The
system task is called at simulation time 0 in the following way:
addbit i1 (a, b, ci, sum, co);
initial
$my_monitor(i1);
Categories: News Groups
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