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Field Programmable Gate Array based computing systems.
Updated: 5 hours 41 min ago
Serial port issues with Matlab
I am using Matlab to communicate with the serial port and the other
end is connected to the FPGA. I am writing data into the serial port
and reading it after a pause which is equal to the time taken by the
data to go to the FPGA and back. I am dividing the image to packets
and sending it in bursts. I am getting a TIME OUT ERROR in matlab. It
end is connected to the FPGA. I am writing data into the serial port
and reading it after a pause which is equal to the time taken by the
data to go to the FPGA and back. I am dividing the image to packets
and sending it in bursts. I am getting a TIME OUT ERROR in matlab. It
Categories: News Groups
ONLINE RESOURCE FOR HELP DESK SOFTWARE
ONLINE RESOURCE FOR HELP DESK SOFTWARE
________________
[link]
________________
[link]
Categories: News Groups
Xilinx Multipass PPR
I've recently started using MPPR to try and get better timing results. I
know there are a lot of "better" way to do it, but if I can MPPR over a
weekend and get the results I need - that's easy and good enough for me.
It seems to me that MPPR is critically flawed in that it only operated on
the results of one specific Map. If the Map seed isn't a very good one, all
know there are a lot of "better" way to do it, but if I can MPPR over a
weekend and get the results I need - that's easy and good enough for me.
It seems to me that MPPR is critically flawed in that it only operated on
the results of one specific Map. If the Map seed isn't a very good one, all
Categories: News Groups
Re: Future architectures [was Re: Intel details future Larrabee ...]
Of course.
Did your component had tristate pins defined as out or inout?
The later, indeed, had problems until relatively recently but the
former always worked as expected.
I, personally, always prefer to have separate in and out ports in
internal components, so I wasn't hit by earlier bugs.
Why they fixed it at the end? I think, the main reason was SOPC
Did your component had tristate pins defined as out or inout?
The later, indeed, had problems until relatively recently but the
former always worked as expected.
I, personally, always prefer to have separate in and out ports in
internal components, so I wasn't hit by earlier bugs.
Why they fixed it at the end? I think, the main reason was SOPC
Categories: News Groups
Format of Actel's SVF files
Hi everyone,
I have a PA3 device on a board where I want to make a quick blank
check to decide if it's neccesary to program or not to program. I use
a JTAG system from Goepel that uses SVF files generated by Actel. The
guy who designed the FPGA can't get me a 'blank check' SVF or a
shortened verify.
I have a PA3 device on a board where I want to make a quick blank
check to decide if it's neccesary to program or not to program. I use
a JTAG system from Goepel that uses SVF files generated by Actel. The
guy who designed the FPGA can't get me a 'blank check' SVF or a
shortened verify.
Categories: News Groups
Weekend DSP + DIP +VLSI front end training starting from 6th September
Arithos Designs is starting a new weekend batch on "Fundamentals of
Digital Signal Processing" and "Fundamentals of Digital Image
Processing" and "Front end VLSI design and simulation" from 6th
September.
For rough outline of the course, please check in our website. The
duration of the Course runs for a month.
Digital Signal Processing" and "Fundamentals of Digital Image
Processing" and "Front end VLSI design and simulation" from 6th
September.
For rough outline of the course, please check in our website. The
duration of the Course runs for a month.
Categories: News Groups
How many mux input on a Xilinx V4 are pratical
Currently I have a design that processes
video data with a number of adjustable
parameters (like window borders) and
process results (like pixel counters).
I seen to have about 28 of them so far,
ranging from binary on/off to 10 bit BCD
counters.
These are displayed on a VGA port or an
NTSC overlay. All these parameters exist
video data with a number of adjustable
parameters (like window borders) and
process results (like pixel counters).
I seen to have about 28 of them so far,
ranging from binary on/off to 10 bit BCD
counters.
These are displayed on a VGA port or an
NTSC overlay. All these parameters exist
Categories: News Groups
How to disable the static routing to cross through the PRR?
Hi! Everyone:
EA PR design flow can allow signals (routes) in the base design to
cross through a partially reconfigurable region without using a bus
macro. Howevr, can I disable the operation? Thanks!
BR,
hunag
EA PR design flow can allow signals (routes) in the base design to
cross through a partially reconfigurable region without using a bus
macro. Howevr, can I disable the operation? Thanks!
BR,
hunag
Categories: News Groups
Mass storage device on ML403 board
Hi there,
I need to implement a mass storage device on this board. My first
approach was using the xilfatfs library for saving the data on a CF
memory, but I'm facing a lot of problems with that. The system turns
pretty unstable, and after some weeks trying to fixed it, we can't
figured out where is the problem. The only guess is that there is a
I need to implement a mass storage device on this board. My first
approach was using the xilfatfs library for saving the data on a CF
memory, but I'm facing a lot of problems with that. The system turns
pretty unstable, and after some weeks trying to fixed it, we can't
figured out where is the problem. The only guess is that there is a
Categories: News Groups
Timing analyser
Hi
Im using timing analyser.
This is a part of my timing report
Data Path: reset to U1/count_9
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tiopi 1.300 reset
reset_IBUF
Im using timing analyser.
This is a part of my timing report
Data Path: reset to U1/count_9
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tiopi 1.300 reset
reset_IBUF
Categories: News Groups
genügt das fürs erste?
Knoppix - Schweizer-Taschenmesser-Linux von CD bootend
[link]
SystenRescueCD - zweites Schweizer-Taschenmesser-Linux [bissle mehr für
Geeks]
[link]
Ultimate Boot CD - drittes Schweizer-Taschenmesser [bissle mehr für Geeks]
[link]
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SystenRescueCD - zweites Schweizer-Taschenmesser-Linux [bissle mehr für
Geeks]
[link]
Ultimate Boot CD - drittes Schweizer-Taschenmesser [bissle mehr für Geeks]
[link]
Categories: News Groups
Virtex 5 bitstream encryption
Hello !
I would like to know the frequency used by Xilinx (Virtex 5) to
decrypt bitstream before configuration .
The decrypter is it slow with small area ? fast with big area ?
unfortunately it's not documented by xilinx .
Thank u for help
I would like to know the frequency used by Xilinx (Virtex 5) to
decrypt bitstream before configuration .
The decrypter is it slow with small area ? fast with big area ?
unfortunately it's not documented by xilinx .
Thank u for help
Categories: News Groups
Genode FPGA graphics project launched
Genode FX is a composition of hardware and software that enables the
creation of fully fledged graphical user interfaces as system-on-chip
solutions using commodity FPGAs, e.g., Xilinx' low-cost Spartan3 series.
The integrated solution complements the Microblaze soft core with custom
hardware for interconnecting display and input devices. On the software
creation of fully fledged graphical user interfaces as system-on-chip
solutions using commodity FPGAs, e.g., Xilinx' low-cost Spartan3 series.
The integrated solution complements the Microblaze soft core with custom
hardware for interconnecting display and input devices. On the software
Categories: News Groups
FPGA/CPLD Design Group on LinkedIn
FPGA/CPLD Design Group on LinkedIn
Group for People Involved In the Design and Verification of FPGA's and
CPLD's to Exchange Idea's and Techniques. You should have FPGA/CPLD
Design/Verification on your Profile to Join. (The focus is more on
FPGA/CPLD in the product as opposed to FPGA's solely as a path to an
Group for People Involved In the Design and Verification of FPGA's and
CPLD's to Exchange Idea's and Techniques. You should have FPGA/CPLD
Design/Verification on your Profile to Join. (The focus is more on
FPGA/CPLD in the product as opposed to FPGA's solely as a path to an
Categories: News Groups
Saving PAR Constraints
Hi
I am doing an iterative design flow and iam using Xilinx 9.2i ISE
I am a newbie in Floorplan and PAR.
I wanted to set some constraints in Floorplanner.
Every time i change a constraint in floorplanner, for example placing
a LUT,
and run PAR the whole placements of other blocks gets changed.
Is it possible to save the constraints generated after PAR..?
I am doing an iterative design flow and iam using Xilinx 9.2i ISE
I am a newbie in Floorplan and PAR.
I wanted to set some constraints in Floorplanner.
Every time i change a constraint in floorplanner, for example placing
a LUT,
and run PAR the whole placements of other blocks gets changed.
Is it possible to save the constraints generated after PAR..?
Categories: News Groups
Side-BUFG, BRAMS and clock routing
Hi everyone,
I've built a small project on the XC3SD1800A kit that receives ethernet
frames and displays their content as a 256x256 4-bit greyscale image via
its VGA port. This uses 16 BRAMS (inferred) as video-ram.
At first the image that got displayed was full of distortions. I also
had hold-time violations of more than 8ns to the address lines of some
I've built a small project on the XC3SD1800A kit that receives ethernet
frames and displays their content as a 256x256 4-bit greyscale image via
its VGA port. This uses 16 BRAMS (inferred) as video-ram.
At first the image that got displayed was full of distortions. I also
had hold-time violations of more than 8ns to the address lines of some
Categories: News Groups
Xilinx Virtex 4 Newbie
I am a complete FPGA newbie.
A friend mentioned that the DS-KIT-4VFX12LC-G from Avnet would be a
good board for learning about FPGAs so I bought it and installed the
ISE 10.1 Webpack.
The website tells me that I have already downloaded my 60 day free
trial of the EDK, but I don't remember downloading it. I don't even
A friend mentioned that the DS-KIT-4VFX12LC-G from Avnet would be a
good board for learning about FPGAs so I bought it and installed the
ISE 10.1 Webpack.
The website tells me that I have already downloaded my 60 day free
trial of the EDK, but I don't remember downloading it. I don't even
Categories: News Groups
xlicmgr vs lmutil/lmstat and floating licenses
Has anyone any experience in using Xilinx floating licenses for IP
cores? I have tried to get a bought license to work for several weeks
now with no success! For interested readers I have pasted in some
commands and printouts below.
****** I work in a Linux environment ******
As You can see the lmutil lmstat command finds the rs_encoder_v6 license
cores? I have tried to get a bought license to work for several weeks
now with no success! For interested readers I have pasted in some
commands and printouts below.
****** I work in a Linux environment ******
As You can see the lmutil lmstat command finds the rs_encoder_v6 license
Categories: News Groups
AES decryption (ASIC)
Hey folks , i need ur opinion about something :
To implement an AES decryption (CBC mode ) algorithm in ASIC , what
would be the best way to do it ? i mean among these architectures
which one do you choose and why :
* Basic iterative architecture
* Partial loop unrolling
* full loop unrolling
* Partia outer-round pipelining
To implement an AES decryption (CBC mode ) algorithm in ASIC , what
would be the best way to do it ? i mean among these architectures
which one do you choose and why :
* Basic iterative architecture
* Partial loop unrolling
* full loop unrolling
* Partia outer-round pipelining
Categories: News Groups
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