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Call for Papers
ISQED 2009, 10th Anniversary of International Symposium on
QUALITY ELECTRONIC DESIGN
March 16-18, 2009. DoubleTree Hotel, San Jose, CA, USA
[link]
Paper Submission Deadline: Oct. 17, 2008
Acceptance Notifications: November 24, 2008
Final Camera-Ready paper: January 2, 2009

Hi,
From the book of Peter's The designer's guide to VHDL, I cannot tell
the difference between attribute: XX'image and to_string. Could anyone
explain that for me? Thanks a lot.

Hi,
I see the following in a VHDL book and some web tutorial. It is used
to detect clk rising edge.
-----------------
if clk'event and clk'value='1' and clk'last_value='0'
then ...
-- to detect setup time
------------------
I think if clk'event(true) and clk'value='1', then clk'last_value will
be '0' unconditionally. That is, "clk'last_value='0'" is redundant. Is

Hi All,
The TimingAnalyzer is a program that can be used for drawing timing
diagrams and performing timing analysis. There is a free version that
anyone can use and a commercial version planned. You can download and
use it now.
I was announcing updates on this newsgroup hoping to find beta testers

I am learning VHDL and one thing i still dont get is how loops are
executed in the vhdl. For, example i have code that will write to a
file for debugging perposes and it is implemented using a while loop:
while word_write_count < 32 loop
write ( trace_line,string'("Address: "));
write ( trace_line,word_write_count);

Call for Papers
IEEE ISQED 2009, 10th Anniversary of International Symposium on
QUALITY ELECTRONIC DESIGN
March 16-18, 2009. DoubleTree Hotel, San Jose, CA, USA
[link]
Paper Submission Deadline: Oct. 17, 2008
Acceptance Notifications: November 24, 2008
Final Camera-Ready paper: January 2, 2009

Does anyone have any opinions on this book? It was recommended by
Clive Maxwell.
were a good
few mistakes. I emailed the professor at his college about a month ago
to see if
he had a site that kept track of the mistakes. He hasn't responded
yet, most likely
on holiday. I have done well with cookbook type texts, so that is why

hello mw

SDF annotation is simple replacement, or it requires an algorhytm
(working with delay paths, etc.)?
Thanks

ONLINE RESOURCE FOR HELP DESK SOFTWARE
________________
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Hi all:
is negative in VHDL free of overflow?
like this
signal din : std_logic_vector(7 downto 0);
.....
when i do
cout <= std_logic_vector(- signed(din));
for example when din equal b"10000000" in complient binary = -128,
after negate it, we got 128 : b"10000000" , is it a overflow? how to
get the right answer? what is the best way to do

Hi!
Can I do this:
if (flag = '1') then
flag <= '0';
....
Thanks!

as there is readmemh in verilog to read a file and put it into
memory... is there any relevant thing in VHDL which can do this.

[link]

Hi,
What is the default value for the last_event attribute? For example
what will be s'last_event when previously no action performed on "s"?
In modelsim it seems it is a very big value.

I've had some curious symptoms with a big pile of code (not all mine) that I'd appreciate the community's inputs regarding (if it's frustrated me, it's probably frustrated the rest of you at some time).
I'm having problems getting consistent behavior in a Modelsim test bench (it did work at some time, but now it seems to generally fail). When I fix it to work in the test bench, then it bombs in synthesis (Modelsim 5.8d, Synplify Pro 8.8.x).

Hi All
Im using ncvhdl version 6.11. For some reason, the uniform function
suddenly does not work as required. The seed value does not change on
different calls to the uniform function. I have debugged my program to
find out the error but have not been successful. So, I have to write a
random generator function (that need not be synthesized). Could

Hi,
I'm new to testbenches so I set a goal to get some examples
to work under ModelSim PE Student Edition 6.4.
I'm trying to do the simplest of things - to simulate a vhdl file.
However once compiled, I have no objects hence nothing that can be added
to the waveform.
I get no errors at all, just no objects after I compile. I see the file

Following is the code... Though in the process "process_count", I have
the signal "count" in the sensitivity list, reset1 is not going to '0'
after the desired count value as is given below in the code. What is
the problem? I am using modelsim.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

Hi,
Is it possible to get back the ".vhd" file which is annotated with
delay values coming from the SDF file?
Now:
...
q_OBUF_D2 : X_AND2
port map (
I0 => a,
I1 => b,
O => q );
...
After that
...
q_OBUF_D2 : X_AND2
generic map (
tipd_I0 => (10.000 ns, 10.000 ns),