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Interop: Xilinx realizes the dream of programmable SDN data planes

One of the major SDN equipment providers claims to have invented software-defined networking in 2009 and from time to time, you'll see that year creep up in its advertising. But a full five years earlier, a 21-year veteran University of Edinburgh professor and Computer Science department head named Gordon Brebner published, with colleagues, a ground-breaking paper on the concept of programming a field programmable gate array, aka FPGA, using a domain-specific language.

That paper involved a then-unheard-of San Jose-based company called Xilinx. Its purpose was to demonstrate how a rudimentary, simple-to-learn language could be implemented for automating network functions on inexpensive hardware. The idea was batted about like a hot potato, never slowing down enough for anyone to get a good enough look: programmable switches.

This week at the Interop conference in Las Vegas, Xilinx finally premiered the full commercial culmination of Brebner's research: Previously called "Softly Defined Networking," Xilinx now calls it SDNet. And while OpenFlow advocates continue to tout the benefits of a programmable control plane, Xilinx adds a tantalizing prospect: the programmable data plane.

In a 2012 presentation (.pdf), Brebner explained why he chose the adverb, ending in "-ly," to describe his system: OpenFlow relies upon a presumption of the respective roles of hardware and software, he said, that are becoming "ossified." Higher-order processors running at slower speeds maintaining the control plane, contrast against lower-order, faster hardware at the switch level handling packet forwarding.

While technologies inspired by OpenFlow have helped extend its level of abstraction into higher levels, Brebner went on, "it is questionable whether the underlying OpenFlow abstraction itself needs to offer such a limited view of forwarding architecture and its programmability, including being tied to existing ossified protocols, given the rather richer programmable capabilities that are actually possible."

In this rich environment, switches should not be constrained by old protocols and assumptions, Brebner argued, but rather opened up with new parameters and possibilities.

Stopping just short of declaring his company's customers as existing in "the real world," Brebner explained that switching hardware is, in practice, far more complex than OpenFlow typically characterizes it, implying that the dumbing-down of switch hardware is not at all the ideal situation, for an SDN or for networks in general. Referring to earlier research demonstrating the viability of 400 Gbps packet parsing applications for a single FPGA array (.pdf), with 1 Tbps just down the road, Brebner concluded it could soon become possible to achieve network programmability such that the behavior of the network--not just the specifications--can be laid down in software, or "soft hardware."

"Soon" ended up coming rather soon for Xilinx--which demonstrated SDNet, its first commercial software-defined data plane environment--this week. The company is promising the capability of so-called "hitless upgrades" to data plane equipment, all while operating at 100% wire speed--at the same time that speed breaks the terabit barrier.

Stated Brebner in 2012: "It is possible to compile high-level network processing descriptions directly and automatically to soft architectures formed from programmable logic that deliver this performance."

While Xilinx is characterizing SDNet as an industry first, there may actually be a race under way for that claim. A few weeks ago, Corsa announced it's in the midst of developing FPGA data planes with the aim of compatibility with OpenFlow 1.3.

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