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Programmable logic: A practical introduction for beginners

Only one sixth of the respondents to a poll we ran last year on Scope Junction reported HDL (hardware definition language, i.e., programmable logic) experience. Thus was this article inspired. If your exposure to this ubiquitous technology has been nil to minimal, or you just want to brush up on the basics and history, read on.

A bit of history

The first practical programmable logic chips, known as PLAs (programmable logic arrays), became available in the mid 1970s. Things really took off though when MMI introduced a simplified series of PLAs they called PALs. Using a basic HDL like PALASM, one could create simple functions, such as address decoders or control logic. Performance was often greater than discrete logic, because many functions that would otherwise need two or more levels of discrete logic could now be accomplished with just one "pass" through the PAL.

Be my PAL

The PAL family continued to evolve into the late 1980s, with faster, lower-power devices, including ones that could be reprogrammed. The most complex device type developed was probably the PAL22V10, which could implement higher-level functions like state machines, and had a more generalized logic array structure than the earlier PALs.
The smaller PALs only allowed for simple AND-OR-based logic, whereas a part like the 22V10 contained registers, tristatable outputs, and so on.

The CPLD

CPLDs (complex programmable logic devices) were the next evolutionary step. These tended to be register-oriented, and sometimes even contained "buried" registers – ones not directly associated with an output pin. Output "macrocells" became relatively sophisticated, and might contain a register, a bunch of configuration and control logic, an XOR gate, and so on.

Because of the increased size of these devices, the logic array tended to get broken into segments. Without this, the AND/OR array would have become unwieldy and slow. Internal signals could travel between these segments, though with some limitations, and also some restrictions on functional change once the pinout was fixed.

An Intel 80486 microprocessor board I designed ca. 1996 used several 64-register CPLDs. One chip would be able to hold several state machines and a significant amount of miscellaneous logic.
Actually, I can stop talking in the past tense, as CPLDs like this are still alive and kicking. They find use whenever an FPGA would be overkill. In fact, a medium-sized CPLD can contain my base-2 log design.

Some parts are actually FPGAs in CPLD clothing. I think this practice is perpetrated by companies to differentiate their RAM-configured FPGAs from their non-volatile "CPLDs."

The FPGA

Xilinx released the FPGA (field-programmable gate array) into the wild ca. 1985, and 25 years later, the FPGA has become virtually synonymous with "programmable logic." The guts of an FPGA is of the "sea of LUTs (lookup tables)" variety. Each of these LUT cells typically contains a flip flop, and yes, a LUT, along with lots of muxes and configuration logic. The LUTs are typically 4- or 5-input, which allows a pretty wide variety of logical behaviors to be described.

These LUTs tend to be arranged in some sort of hierarchy – an arrangement that allows for practical handling of signal routing. Fortunately, we rarely need concern ourselves with such details. That's the design software's problem.

FPGAs these days often include other features, such as PLLs and clock management blocks, high-speed serial transceivers (the range today being about 3-30Gb/s), RAM (a large chip might have megabytes), DSP blocks (hundreds or even thousands of multipliers are not unheard of!), and PCIe interfaces.

There are also "mixed-domain" FPGAs. Several manufacturers have parts with one or two microprocessors on-chip, analog peripherals, or both.
Not to fear if your FPGA has no processor. You can instantiate as many "soft-core" processors as will fit in the programmable logic. Even a mid-range FPGA can hold dozens of 32-bit processors!

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