MOS-AK/GSA Modeling Working Group Holds Spring Workshop in Dresden
Experts Share Insight on Compact Device Modeling with Emphasis on Simulation-Aware Models
SAN JOSE, Calif. (May 7, 2012) - The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, held its annual spring workshop on April 26-27, 2012 at the Design Automation Division EAS of the Fraunhofer Institute for Integrated Circuits IIS in Dresden, Germany. More than 50 international academic researchers and modeling engineers attended four sessions to hear 16 technical compact modeling talks and poster presentations. The MOS-AK/GSA Modeling Working Group organized the event supported by Joachim Haase Fraunhofer IIS/EAS in Dresden, and a complementary X-FAB clean room visit, poster session and open networking event was hosted by Alexander Petr, X-FAB in Dresden.
The workshop's three sessions focused on the advanced compact modeling for analog/RF, high-voltage metal-oxide semiconductor (HVMOS) IC design application, computer-aided design (CAD)/EDA simulations highlighting recent development of the open source CAD tools. Invited international modeling experts presented: Verilog-A implementation of a photodiode model with spectral responsitivity in the open source simulator ngspice; EKV modeling of MOS varactors and LC tank oscillator design; transistor modeling with Modelica; advanced and beyond-CMOS FET technologies for RF IC design; theory of the junctionless UTB SOI-FET; modeling of high power (HV) discrete MOSFETs and flicker noise modeling in HV MOSFETs; interference and distortion Analysis for nonlinear analog circuits; physics-based modeling of MOS devices time-dependent variability for circuit simulation, moving variability from devices to higher levels of abstraction; a method for CMOS IC design towards yield optimization; problems with combining PSpice and Spectre for PCB and IC joint simulation; analytical DC model of double-gate (DG) p-channel MOSFETs adapted to advanced transport models; a turn-key solution for end-to-end silicon device modeling flow; challenges in modeling a power lateral PNP device; development and implementation of COMON compact models in industries. Embedded high-quality technical poster presentations covered compact model development, implementation, deployment, device-level circuit simulations and model standardization.
As a result of an unfolded compact modeling discussion, the MOS-AK Group followed recommendation of Alexander Petr, X-FAB, a member of the Extended MOS-AK/GSA Compact Modeling Committee, to create a compact modeling open directory (CMOD). The directory will list available SPICE/Compact models including Verilog-A models for an extensive range of the semiconductor devices. The MOS-AK/GSA Group believes that the CMOD initiative will also stimulate further compact model developments for inter domain technologies and multidisciplinary applications.
The MOS-AK/GSA Modeling Working Group coordinates several upcoming modeling events: a special compact modeling session at the MIXDES Conference in Warsaw, Poland; COMON Training Course in Tarragona, Spain; an autumn Q3 MOS-AK/GSA workshop in Bordeuox, France; and a winter Q4 MOS-AK/GSA meeting in San Francisco, CA, USA.
About Fraunhofer IIS/EAS in Dresden, Germany:
The Design Automation Division EAS in Dresden is part of the Erlangen-based Fraunhofer-Institute for Integrated Circuits IIS. Headed by Dr. Peter Schneider, the division performs R&D activities aiming at computer-aided design of electronic and heterogeneous systems. At the same time, Fraunhofer IIS/EAS is a partner to industry in the fields of microelectronics, microsystems technology and mechatronics. The EAS Division in Dresden is one of the largest research institutions in the field of design automation in Europe.
X-FAB is the leading analog/mixed-signal foundry group manufacturing silicon wafers for analog-digital integrated circuits (mixed-signal ICs). X-FAB maintains wafer production facilities in Erfurt and Dresden (Germany); Lubbock, Texas (U.S.); and Kuching, Sarawak (Malaysia); and employs approximately 2,400 people worldwide. Wafers are manufactured based on advanced modular CMOS and BiCMOS processes with technologies ranging from 1.0 to 0.13 micrometers, for applications primarily in the automotive, communications, consumer and industrial sectors.
About MOS-AK/GSA Modeling Working Group:
In 2009, GSA merged its efforts with MOS-AK, a well-known industry compact modeling volunteer group primarily focused in Europe, to re-activate its Modeling Working Group. The Modeling Working Group plays a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact model standardization and related tools for model development, validation/implementation and distribution.
The Global Semiconductor Alliance mission is to accelerate the growth and increase the return on invested capital of the global semiconductor industry by fostering a more effective ecosystem through collaboration, integration and innovation. It addresses the challenges within the supply chain including IP, EDA/design, wafer manufacturing, test and packaging to enable industry-wide solutions. Providing a platform for meaningful global collaboration, the Alliance identifies and articulates market opportunities, encourages and supports entrepreneurship, and provides members with comprehensive and unique market intelligence. Members include companies throughout the supply chain representing 30 countries across the globe.