DAC panel debates: Are FPGAs ready to replace ASICs?
ASIC development costs are rising, which make FPGAs an attractive and advantageous alternative - in some cases.
At the 2012 Design Automation Conference (DAC) in San Francisco on June 5, representatives from FPGA vendors Xilinx and Altera faced off against ASIC designers from Huawei Technologies, Juniper Networks, IBM, and Advantest to present their case for or against the question, “Will Your Next ASIC Ever Be an FPGA?” FPGAs have long been used as an intermediate step to higher volume ASICs, and vendors such as Altera have even formalized the migration process in their “HardCopy” offering. More recently, vendors have developed FPGA SoCs by adding embedded ARM Cortex processor systems to programmable logic, providing designers with more alternatives to developing their own application-specific silicon. But, can this new generation of devices do everything an ASIC can do?
The spectrum of FPGA support
At DAC, Brent Przybus, Director of FPGA Products at Xilinx, said that changes are occurring that shift the balance in the FPGA-ASIC decision-making process. Global competition is driving increased demand for shorter Time To Market (TTM), he said, which can be met with the higher performance and instant access to technology of today’s FPGAs. Przybus acknowledged that the first issue most designers think of when considering FPGAs is higher unit cost, but he argued that FPGAs have an advantage in much lower development cost. By eliminating the Non-Recurring Expenses (NRE) of an ASIC and gaining early market share, overall system profitability can be higher with FPGAs, according to Przybus.
John Costello, VP of IC Design at Altera, positioned FPGAs in the middle, between General-Purpose Processors (GPPs) and ASICs/ASSPs. FPGAs have evolved to offer the best of both of these worlds, he said, as system designers must weigh the need for flexibility versus efficiency, along with cost, power consumption, and performance. Costello touted the capabilities of the new FPGA SoCs and “silicon convergence,” which enables designers to build mixed systems that integrate microprocessors with DSPs, programmable logic, and high-speed interfaces. In response to the FPGAs replacing ASICs question before the panel, Costello said it has already happened.
Huawei Technologies’ VP of Engineering, Bill Lynch, followed Altera on the DAC panel, saying that his company uses all three alternatives, ASICs, FPGAs, and GPPs, depending on the application. However, he challenged the premise put before the panel, arguing that rather than ASICs versus FPGAs, the question should have been whether ASICs would be replaced by some form of programmable (rather than general-purpose) processor, To that point, Lynch said his answer would be a definite yes.
The appeal of both
David Ofelt, a Distinguished Engineer at Juniper Networks, presented strong arguments both for and against ASICs and FPGAs. While FPGAs have benefited from continued scaling according to Moore’s Law, Ofelt pointed out that FPGA logic gates and memory blocks inevitably suffer in comparison to ASICs because of the high overhead required to implement programmability. ASICs have the advantage in this area because they use 100 percent of their gates to perform useful work, said Ofelt. Juniper’s designs require large amounts of DRAM and 2x the number of Serializer/Deserializers (SERDES) that FPGAs offer. Ofelt also criticized FPGA Input-Outputs (I/Os), which he said suffer from a “Swiss Army knife” problem. He also rejected the system profitability argument put forth by Xilinx because of the way various costs are accounted for at most companies, explaining that NRE expenses are a “sunk cost” whereas the high unit costs of FPGAs affect margins, which is how companies calculate profitability of product lines.
On the pro-FPGA side, Ofelt said that FPGAs offer a great replacement for “yesterday’s ASIC,” and that Juniper often uses FPGAs to replace older designs. In high-margin applications, and especially in low volume, FPGAs are useful for lower bandwidth designs. Other advantages that Ofelt attributed to FPGAs included avoiding the one-quarter latency from ASIC tapeout to silicon and eliminating NRE costs. FPGA design projects also have the advantage of being able to release to various team members once certain stages of development have been completed, whereas ASICs typically require completely working silicon.
The limits that lead to FPGA opposition
Jeanne Trinko Mechler, a Distinguished Engineer at IBM, presented the strongest argument against FPGAs, with a very detailed breakdown of the reasons FPGAs cannot compete with ASICs. She provided this analysis of the typical content in a custom chip at IBM.
Typical IBM ASIC chip content:
· 23 percent DRAM
· 29 percent arrays of TCAM, SRAM, ROMs, and register files
· 10 percent processor cores, interface busses, communication PHYs, and analog blocks.
· 14 percent logic
· 8 percent latches
· 9 percent high-speed SERDES
· Miscellaneous: 2 percent test logic, 1percent fuses, and 4 percent deep-trench decoupling capacitors.
Mechler said that there is an increasing amount of silicon IP available for FPGAs, but it is still not comparable to what is available for ASICs. At IBM, she said, FPGAs are used for prototyping and then migrated to ASICs. Comparing a 32 nm ASIC to a 28 nm FPGA, Mechler asserted that ASICs offer a 50:1 advantage in logic density at approximately 50 million cells, versus 400 thousand to 2 million in the most advanced FPGAs. She also graded ASICs and FPGAs on memory content (a 15:1 advantage ASIC), IP for transceivers, DDR3 and PCIe interfaces (even), and DSP content – which she also called even. Mechler also claimed ASIC advantages in Design For Test (DFT), ability to use voltage islands for sophisticated power management, and the ability to use Formal Verification methods.
The IBM methodology, as presented by Mechler, is highly optimized for ASIC design, so the rigorous breakdown by the numbers should be viewed with that bias in mind; Leading edge ASIC designs will always achieve higher core clock frequencies (1 GHz versus 250 MHz in the IBM analysis), but FPGAs are designed more for parallelism, requiring a different methodology. She concluded by acknowledging that FPGAs require a much smaller “back-end” (physical design) effort, and that the flexibility to change hardware and firmware quickly is of great benefit in prototyping “if the content and performance fits the product.” As for FPGA SoCs, Mechler expressed her opinion that once you have a hardened ARM core it is no longer an FPGA, but an ASIC.
Fitting the right approach to the right application
Perhaps, as Huawei’s Lynch argued, asking if FPGAs can replace ASICs is the wrong question. They are necessarily different beasts. It is somewhat like asking if a screwdriver can replace a hammer. Sure, if you really need to, but they each are best utilized in the ways for which they are optimized. Companies that serve very high volume markets with highly customized silicon know very well how to optimize their designs down to the most minute detail. They can amortize the much higher costs of ASIC development over a high volume of sales. This is, as Xilinx and Juniper revealed, more of an unfortunate accounting issue than a technical one. For other companies targeting smaller volume applications, FPGAs can provide a more cost-effective alternative.
The debate at DAC does serve to highlight some of the challenges that FPGA vendors, and the supporting EDA tool providers, face in growing the FPGA market. Tools and methodologies are needed to exploit parallelism and not just push the limits of timing closure, which is the focus of typical ASIC design flows. More advancements are also needed to seamlessly port large HDL designs, which can exceed a single FPGA’s capacity, to multiple FPGAs. Fortunately, several exhibitors at DAC showed developments in this area, as well as other tools for FPGA prototyping. As the expenses of developing an ASIC in advanced process nodes continue to rise, the use of FPGAs as an alternative will become more and more advantageous.