Altera’s Quartus II Software Version 11.1 Delivers Arria V and Cyclone V FPGA Support and Productivity Improvements
San Jose, Calif., November 7, 2011—Altera Corporation (Nasdaq: ALTR) today announced the release of its Quartus® II software version 11.1, the industry’s number one design software in performance and productivity for CPLD, FPGA and HardCopy® ASIC designs. This latest software release features expanded support for Altera’s 28-nm FPGAs, including compilation support for Arria® V and Cyclone® V FPGAs and enhanced support for Stratix® V FPGAs. Quartus II software version 11.1 also includes added support for Altera’s system-level debug tool, System Console. System Console raises the level of abstraction for debugging and works in tandem with low-level debug tools, such as Altera’s SignalTap™ II embedded logic analyzer, to significantly reduce verification time.
“Support for Arria V and Cyclone V FPGAs allows designers to meet performance requirements and achieve the lowest power in the industry at 28 nm, while lowering system cost in a wide range of applications,” said Alex Grbic, Altera’s director of software, DSP and IP marketing. “This new version of the Quartus II software allows customers to quickly design, verify and debug their 28-nm designs using the latest in system-level design tools.”
Quartus II software version 11.1 features compilation support for Arria V FPGAs and Cyclone V FPGAs. Arria V FPGAs deliver a balance of power, performance and system cost for midrange applications. Cyclone V FPGAs provide the lowest power and lowest system cost in a 28-nm FPGA. This release also provides additional support for Altera’s high-end 28-nm Stratix V FPGAs, including PCI Express® PCIe® Gen3 support and bitstream generation capability for DDR3/QDRII memories.
The configurable and interactive System Console tool included with the Quartus II software version 11.1 satisfies a wide range of system debug needs. System Console allows designers to analyze and interpret data and monitor the performance of a system under real-world conditions. Based on TCL, designers using System Console can quickly build verification scripts or custom graphical user interfaces in an advanced programming environment, enabling sophisticated instrumentation and verification solutions for Qsys systems. This tool—which is designed for simulation, lab testing and deployment phases of a design—requires minimal resources and reduces the number of hardware compilation steps, improving designer productivity.
Additional Features Within Quartus II Software Version 11.1 Include:
- Transceiver Toolkit—Quartus II software version 11.1 supports the on-chip EyeQ signal quality monitoring feature in Stratix V FPGA transceivers, enabling users to analyze the post-equalized transceiver eye and achieve optimal signal quality and lower BER.
- Qsys Enhancements—This release adds expanded support for third-party simulation tools and also includes preliminary support for the ARM® AMBA® AXI™ protocol.
- SoC Design Environment—Quartus II software version 11.1 includes a preview of an integrated SoC design environment that uses hardware/software co-design with Altera’s SoC FPGAs to accelerate the design process, enabling customers to maximize their productivity by using familiar tools and development flows for both processor and FPGA development.
Pricing and Availability
Both the Subscription Edition and the free Web Edition of Quartus II software version 11.1 are now available for download. Altera's software subscription program simplifies obtaining Altera design software by consolidating software products and maintenance charges into one annual subscription payment. Subscribers receive Quartus II software, the ModelSim-Altera Starter edition and a full license to the IP Base Suite, which includes 14 of Altera's most popular IP (DSP and memory) cores. The annual software subscription is $2,995 for a node-locked PC license and is available for purchase at Altera's eStore.
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