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Browse resumes of FPGA Designers

Anirudh's CV

Submitted by anirudh on February 7, 2012 - 5:41pm

Phone: 040-27053161
Mobile No: 8019544350
Email: [email protected]

Address: H.No: 9-18,VENKATESWARA NAGAR,
MALKAJGIRI,HYDERABAD,
ANDHRA PRADESH,
INDIA.

Objective

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Anirudh's CV

Submitted by anirudh on February 7, 2012 - 5:41pm

Phone: 040-27053161
Mobile No: 8019544350
Email: [email protected]

Address: H.No: 9-18,VENKATESWARA NAGAR,
MALKAJGIRI,HYDERABAD,
ANDHRA PRADESH,
INDIA.

Objective

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FPGA Verification Engineer

Submitted by rlrice64 on January 31, 2012 - 2:27pm

Robert L. Rice Jr.
3375 Apache Court – Allentown, Pennsylvania 18104

Home: (610) 799 – 6492 [email protected]

Quality Assurance/Verification Engineer

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FPGA software and hardware Verification and Validation

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M.Tech (VLSI DESIGN AND EMBEDDED SYSTEMS) with 2.5 year experience

Submitted by krish_india18 on January 22, 2012 - 10:15pm

KRISHNASA PAWAR
Permanent address: S/0 PARASHURAMSA PAWAR
HOSPET CHOWK, VIDYARANYA ROAD
GADAG-BETGERI Email Id: [email protected]

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FPGA synthesis

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M.Tech (VLSI DESIGN AND EMBEDDED SYSTEMS) with 2.5 year experience

Submitted by krishnapawar on January 6, 2012 - 4:07am

KRISHNASA PAWAR
Permanent address: S/0 PARASHURAMSA PAWAR
HOSPET CHOWK, VIDYARANYA ROAD
GADAG-BETGERI Email Id: [email protected]

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FPGA design and functional verification

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YOUNG EMBEDDED ENGINEER

Submitted by Delcroip on November 16, 2011 - 3:15am

Patrick Delcroix, age:25

Address:542 rue de Lorette,
45160 Olivet, France
@ [email protected]
Phone: +336.28.25.58.48

Electronic and Software engineer

Education
- 2005-2011 Engineering school at Polytech'Orléans.
  Electronic Signal Image

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VLSI Design Engineer ( Front End )

Submitted by atul.dekate on November 4, 2011 - 2:41am

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FPGA Design/Verification Engineer

Submitted by suman0316 on October 30, 2011 - 11:42pm

Suman Boppana
134 Gunseo-ri, Jiksan-eu, Seobuk-gu Cheonan, Chungnam. 331-881, South Korea,
Mobile:+821076636530

Location: South Korea
Phone: +821076636530
Email: [email protected]
Alternate Email: Not specified Date of Birth: 16 Mar 1983
Gender: Male
Nationality: India
Language: ,English,Hindi,Telugu,

FPGA/ASIC Design/Verification Engineer with 6+ yea...

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hardware engineer

Submitted by gehatzip on October 26, 2011 - 7:14am

George Chatziparaskevas

Education
- M.Sc. in Electronic and Computer Engineering
  GPA: 9.17/10. Department of Electronic and Computer Engineering - Technical University of Crete, Greece (2 years course 2009 - 2010).

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PhD & Research profile, 3yrs experience with FPGAs for HPC and FPGA-based prototyping, parallel sw development C/C++ w/ Pthreads/MPI. Europe

Submitted by simosec on October 19, 2011 - 10:50pm

Currently a PostDoc Researcher @ Pacific Northwest National Lab, Richland, WA, USA. Working on HPC architectures and FPGA-based ISA extensions for irregular applications (graph-based). Mainly working on massively multithreaded machines like the Cray XMT. I am also developing experience with other machines (Convey HC-1 for FPGA-based acceleration and Tilera Tile64).

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