Home
World's Largest FPGA/CPLD Portal


edk

Graduate M.Sc. Electronic and Computer Engineer Graduate, Xilinx, VHDL, Virtex-2 Pro and Virtex-5 Design, CPLD Design - Europe

Georgios-Grigorios Mplemenos
M.Sc. Electronic and Computer Engineer
____________________________________________________________________

Contact Information

zermelo's picture

3 yrs expertise, Xilinx, VHDL, Virtex-4 verification and re-design, Barcelona, Spain

Name: Jose Manuel Address: Diputación St., num. 135, main floor , 1st door.

Surnames: Caballero Pérez Postal Code: 08011

Embedded Digital Systems Engineer

Eyyub Can ODACIOGLU
Room 18s Stanmer Court, Lewes Road
BN1 9PU Falmer, Brighton UK
Mobile Phone UK: +447789518452 Mobile Phone Turkey: +905554206888

Facebook  Twitter  Linkedin  Orkut  YouTube      RSS

Check out FPGA related videos

Find Us On Facebook