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C
Determistic & Challenging
Submitted by
YASH
on April 1, 2011 - 1:03pm
 
Tags:
C
Cadence
Comsol
MATLAB
systemC
Tanner
Verilog
Read more
8yrs experience, Xilinx, VHDL, France / Spain
Submitted by
csantos
on January 22, 2011 - 2:08am
Cayetano SANTOS
Tags:
C
FPGA
ISE Design Suite
LabView FPGA
MATLAB
Modelsim
Scilab
Synplify Pro
VHDL
Xilinx
Read more
Senior Hardware Design Engineer/Project Manager
Submitted by
emadamsfl
on December 16, 2010 - 10:54am
Normal
0
false
Tags:
Assembly Languages
C
Chipscope
ClearCase
CVS
FPGA
Kermit K95 Scripting
Linux
Makefile
Mentor Capture
Mentor Synthesis
Microsoft Project
Modelsim
Orcad Capture
PCIX
Project Management
Simulation
SVN
Verilog
VHDL
Windows Desktop Tools
Xilinx
XPS
Read more
10 years experience FPGA/ASIC design for wireless communications, networking, network testing, and radar signal processing
Submitted by
kanglc
on October 28, 2010 - 10:43pm
Kang Liat Chuan
Summary
Tags:
asic
C
DC
FPGA
Matlab. Cocentric
Microchip
Microcontroller
Modelsim
PERL
Synopsys
Synplify
Tcl/tk
VHDL
Vim
Xilinx
Read more
10 years experience FPGA/ASIC design for wireless communications, networking, network testing, and radar signal processing
Submitted by
kanglc
on October 28, 2010 - 10:40pm
Kang Liat Chuan
Summary
Tags:
asic
C
DC
FPGA
Matlab. Cocentric
Microchip
Microcontroller
Modelsim
PERL
Synopsys
Synplify
Tcl/tk
VHDL
Vim
Xilinx
Read more
B.E (ELECTRONICS) ENGINEER
Submitted by
urvish08
on October 7, 2010 - 9:07am
Tags:
8051
8085
C
C++
MATLAB
Read more
FPGA Design Engineer
Submitted by
Antim
on August 4, 2010 - 10:29pm
Tags:
AHDL
base knowledge of ISE (Xilinx)
base knowledge of NIOSII with SOPC
C
Modelsim
Quartus
VHDL
Read more
4 years of FPGA as well as high speed transceivers DFT experience at Altera - San Jose,CA
Submitted by
ramry01
on March 14, 2010 - 8:53pm
Tags:
C
C++
Design Compiler and hspice
PERL
Quartus
TCL
Tetramax
VCS
Verilog
8 years experience in Xilinx FPGA/ASIC design/Digital IC design
Submitted by
chrisdekoh
on March 7, 2010 - 7:35am
Tags:
amba
ARM7
C
Core-generator
Design Compiler
edk
ISE
Modelsim
Nc-affirma
PERL
Primetime
UNIX
Verilog
VHDL
Xilinx
Read more
Sr FPGA Design and Verification Engineer
Submitted by
ishwarayya
on February 11, 2010 - 8:02am
Tags:
Assembly
C
TCL
Verilog
VHDL
Read more
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