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C1394A: IEEE-1394a Link Layer Controller Core |
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ATA-4 Host Controller |
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ATA-5 Host Controller |
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8052 Compatible Microcontroller |
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8051 RISC Microcontroller |
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I2C Bus Controller |
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8051 Base Compatible Microcontroller |
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7:1 LVDS Video Interface for LatticeECP2/M |
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16750 UART w/ FIFOs |
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DDR2 SDRAM Controller - Pipelined |
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8b/10b Encoder/Decoder |
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Turbo Convolutional Code Decoder, CDMA2000/3GPP2 |
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Turbo Product Code |
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Tri-Mode Ethernet Media Access Controller (TEMAC) |
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V3.0 PCI 32-bit/(66-33 MHz) Core and Design Kit |
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Util Bus Split Operation |
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V3.0 PCI 64-bit/(66-33 MHz) and PCI 32-bit/(66-33 MHz) Core |
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Util Flop-Flop |
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Util Reduced Logic |
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Util Vector Logic |
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SPI-3 (PL3) Link Layer Interface, 4-channel |
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Synchronous FIFO |
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SPI-3 Link Layer Interface, Multi-channel |
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SPI-3 (PL3) Link Layer Interface, 1-channel |
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SPI-3 Physical Layer Interface, Multi-channel |
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System Monitor Wizard |
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SPI-3 (PL3) Link Layer Interface, 2-channel |
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SPI-4 Phase 2 Interface Solutions |
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UMTS/3GPP Turbo Convolutional Decoder |
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Viterbi Decoder, (IEEE 802-Compatible) |
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WiMAX FEC Pack |
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Virtex-5 RocketIO GTP Wizard |
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XAUI |
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Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper |
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VLYNQ Interface for Texas Instruments Processors |
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Viterbi Decoder |
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Virtex-4 RocketIO Wizard |
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Single-Port Block Memory |
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Virtex-5 Cyclic Redundancy Check |
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Sine Cosine Look Up Table |
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