FPGA Central

I am trying to instantiate a Xilinx Asynchrouns FIFO with coregen and
am running into problems. Here is what I have for the control
signals

wr_clk is running at 6 MHz
rd_clk is running at 48 MHz

wr_en <= not almost_full;

process(rd_clk)
begin
if(rd_clk'event and rd_clk = '1')
rd_en <= not almost_empty;
end if;
end process;

The code is simple however, I can tranfer are 180K and the thing
dies. Anyone out there who has used the Async FIFO from Corgen and
gotten it to work?

Regards

Try this:

> process(rd_clk, almost_empty)

Brad Smallridge

"Brad Smallridge" <[email protected]> wrote in message
news:[email protected]..
> Try this:
>
>> process(rd_clk, almost_empty)
>
Don't bother to try this, it is not correct. The sensitivity list that you
have for your process is correct (i.e. just rd_clk).

KJ

> Don't bother to try this, it is not correct. The sensitivity list that
> you have for your process is correct (i.e. just rd_clk).

Yeah, you are right. I don't know what I was thinking.

Or maybe I was thinking that:
>rd_en <= not almost_empty;
should not be clocked at all, so that

process(almost_empty)
begin
-- if(rd_clk'event and rd_clk = '1')
rd_en <= not almost_empty;
-- end if;
end process;

is what he should use.

Brad