FPGA Central

During synthesis and pre layout timing analysis, we assume a certain
wire load model for the interconnect for delay estimates.

Queries:

1. Is only the wire load model *type* assumed or are there any
assumptions made on the *lengths* of interconnects too.

2. Does the synthesis tool and STA tool influence the placement
and layout (because of the delay estimates) in any way.

I am trying to figure out how zero timing violations in synthesis and
STA is sufficient to *guarantee* that there will not be any timing
violations during PAR.

Thanks,
Anand

On Thu, 22 Apr 2004 12:11:40 +0530, "Anand P. Paralkar"
<[email protected]> wrote:

>I am trying to figure out how zero timing violations in synthesis and
>STA is sufficient to *guarantee* that there will not be any timing
>violations during PAR.

Wireload models are only an estimate and at finer geometries not a
very good one either. After PAR is done, you need to extract the exact
RC loads of the wires and do the STA again to make sure there are no
violations left. Hopefully there won't be too many and you can fix
them easily without major disruptions to the placement.

Kal,

How does the synthesis tool and STA tool ensure that "there won't be too
many" violations and "you can fix them easily without major disruptions
to the placement"?

Thanks,
Anand

kal wrote:
> On Thu, 22 Apr 2004 12:11:40 +0530, "Anand P. Paralkar"
> <[email protected]> wrote:
>
>
>>I am trying to figure out how zero timing violations in synthesis and
>>STA is sufficient to *guarantee* that there will not be any timing
>>violations during PAR.
>
>
> Wireload models are only an estimate and at finer geometries not a
> very good one either. After PAR is done, you need to extract the exact
> RC loads of the wires and do the STA again to make sure there are no
> violations left. Hopefully there won't be too many and you can fix
> them easily without major disruptions to the placement.
>

"Anand P. Paralkar" <[email protected]> wrote in message news:<[email protected]>...
> During synthesis and pre layout timing analysis, we assume a certain
> wire load model for the interconnect for delay estimates.
>
> Queries:
>
> 1. Is only the wire load model *type* assumed or are there any
> assumptions made on the *lengths* of interconnects too.

Wire Load model statistically defines the length of wire as a function
of:
1. Size (area) of the block encapsulating the wire
2. Fanout of the wire.

Note, that synthesis & STA blocks hierarchy should match PAR blocks
hierarchy in order to get the right area for (1)

Then, wire delay is calulated as a linear function of the wire length.



> 2. Does the synthesis tool and STA tool influence the placement
> and layout (because of the delay estimates) in any way.

Sythesis tool generates the netlist topology. Different topologies -
different PAR results
STA tool provides timing contraints. In a case of timing-driven PAR,
timing constraints influence on PAR results as well.

Regards,
Alexander Gnusin

Anand P. Paralkar wrote:


> I am trying to figure out how zero timing violations in synthesis and
> STA is sufficient to *guarantee* that there will not be any timing
> violations during PAR.

There are no guarantees with synthesis timing estimates
before place and route. Consider a 100% synchronous
design and an fmax constraint the place and route
static timing.

-- Mike Treseler

On Thu, 22 Apr 2004 13:25:21 +0530, "Anand P. Paralkar"
<[email protected]> wrote:

>Kal,
>
>How does the synthesis tool and STA tool ensure that "there won't be too
>many" violations and "you can fix them easily without major disruptions
>to the placement"?
>
>Thanks,
>Anand
>
>kal wrote:
>> On Thu, 22 Apr 2004 12:11:40 +0530, "Anand P. Paralkar"
>> <[email protected]> wrote:
>>
>>
>>>I am trying to figure out how zero timing violations in synthesis and
>>>STA is sufficient to *guarantee* that there will not be any timing
>>>violations during PAR.
>>
>>
>> Wireload models are only an estimate and at finer geometries not a
>> very good one either. After PAR is done, you need to extract the exact
>> RC loads of the wires and do the STA again to make sure there are no
>> violations left. Hopefully there won't be too many and you can fix
>> them easily without major disruptions to the placement.
>>

STA is just an analysis tool; normally synthesis tools have their own
internal STA capability and they can't "ensure" anything. If you
notice I said "hopefully there won't be ..." If you want better
results, instead of using a strictly logic synthesis tool, you should
use one (ie PKS or Physical Compiler) which can read a physical
library (LEF) and try to make better estimates of the parasitic loads.
To get the final results, you always have to run an extraction tool
(simplex, starrcxt etc), back-annotate the spf and run STA again.