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  #1 (permalink)  
Old 07-10-2008, 12:00 PM
bigyellow
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Default What does the sharp sign mean in VHDL?

for example, In the code

constant A : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(16#12#, 8);

what does the 16#12# mean here?
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  #2 (permalink)  
Old 07-10-2008, 12:23 PM
Jonathan Bromley
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Default Re: What does the sharp sign mean in VHDL?

On Thu, 10 Jul 2008 03:00:19 -0700 (PDT), bigyellow wrote:


> constant A : std_logic_vector(7 downto 0) :=
>conv_std_logic_vector(16#12#, 8);
>
>what does the 16#12# mean here?


Hex radix, like "0x12" in C, or "'h12" in Verilog.

Also

2#010010# -- binary
8#22# -- octal
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
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  #3 (permalink)  
Old 07-10-2008, 12:55 PM
Brian Drummond
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Default Re: What does the sharp sign mean in VHDL?

On Thu, 10 Jul 2008 11:23:01 +0100, Jonathan Bromley
<[email protected]> wrote:

>On Thu, 10 Jul 2008 03:00:19 -0700 (PDT), bigyellow wrote:
>
>
>> constant A : std_logic_vector(7 downto 0) :=
>>conv_std_logic_vector(16#12#, 8);
>>
>>what does the 16#12# mean here?

>
>Hex radix, like "0x12" in C, or "'h12" in Verilog.
>
>Also
>
> 2#010010# -- binary
> 8#22# -- octal


And, of course, 6 * 9 = 13#42#

(though I haven't tried base 13 in synthesis)

- Brian
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  #4 (permalink)  
Old 07-10-2008, 01:03 PM
Jonathan Bromley
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Default Re: What does the sharp sign mean in VHDL?

On Thu, 10 Jul 2008 11:55:03 +0100, Brian Drummond wrote:

>And, of course, 6 * 9 = 13#42#


But if everything is answered, what's the point of Usenet?

Seriously OT: I've known that relationship for some time,
but I've never seen any evidence to say whether or not
Douglas Adams did it deliberately - I had always assumed
he was far too smart for it to be an accident, but...
do you have any references for that?

OT2: How many examples are there of digit-strings N, M
such that M /= N and N#M# = M#N# ???
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
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  #5 (permalink)  
Old 07-10-2008, 03:13 PM
Tricky
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Default Re: What does the sharp sign mean in VHDL?


>
> OT2: How many examples are there of digit-strings N, M
> such that M /= N and N#M# = M#N# ???
> --


off the top of my head:

10#2# = 2#10 = 2
10#3# = 3#10 = 3
etc, forever
(1#10# is not a legal representation)

also, any combination of 11-19, eg 11#19 = 19#11, 13#16#

After this, differences gradually diverge, eg
11#20# = 22, 20#11# = 21 diff = 1
11#21# = 23, 21#11# = 22 diff = 1
.....
12#20# = 24, 20#12# = 22 diff = 2
12#21# = 25, 21#12# = 23 diff = 2
......
etc


so assuming thats all of them, then 56 + (infinity: 10#N#, N#10# where
N /= 0, 1 or 10)

I really ought to get back to work.
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  #6 (permalink)  
Old 07-12-2008, 12:10 AM
diogratia
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Default Re: What does the sharp sign mean in VHDL?

On Jul 11, 1:13 am, Tricky <Trickyh...@gmail.com> wrote:
> > OT2: How many examples are there of digit-strings N, M
> > such that M /= N and N#M# = M#N# ???
> > --

>
> off the top of my head:
>
> 10#2# = 2#10 = 2
> 10#3# = 3#10 = 3
> etc, forever
> (1#10# is not a legal representation)
>
> also, any combination of 11-19, eg 11#19 = 19#11, 13#16#
>
> After this, differences gradually diverge, eg
> 11#20# = 22, 20#11# = 21 diff = 1
> 11#21# = 23, 21#11# = 22 diff = 1
> ....
> 12#20# = 24, 20#12# = 22 diff = 2
> 12#21# = 25, 21#12# = 23 diff = 2
> .....
> etc
>
> so assuming thats all of them, then 56 + (infinity: 10#N#, N#10# where
> N /= 0, 1 or 10)
>

Not in VHDL:

13.4.2 Based literals

A based literal is an abstract literal expressed in a form that
specifies the base explicitly. The base must be at least two and at
most sixteen.


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  #7 (permalink)  
Old 07-12-2008, 12:11 AM
diogratia
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Posts: n/a
Default Re: What does the sharp sign mean in VHDL?

On Jul 11, 1:13 am, Tricky <Trickyh...@gmail.com> wrote:
> > OT2: How many examples are there of digit-strings N, M
> > such that M /= N and N#M# = M#N# ???
> > --

>
> off the top of my head:
>
> 10#2# = 2#10 = 2
> 10#3# = 3#10 = 3
> etc, forever
> (1#10# is not a legal representation)
>
> also, any combination of 11-19, eg 11#19 = 19#11, 13#16#
>
> After this, differences gradually diverge, eg
> 11#20# = 22, 20#11# = 21 diff = 1
> 11#21# = 23, 21#11# = 22 diff = 1
> ....
> 12#20# = 24, 20#12# = 22 diff = 2
> 12#21# = 25, 21#12# = 23 diff = 2
> .....
> etc
>
> so assuming thats all of them, then 56 + (infinity: 10#N#, N#10# where
> N /= 0, 1 or 10)
>
> I really ought to get back to work.


Not in VHDL:

13.4.2 Based literals

A based literal is an abstract literal expressed in a form that
specifies the base explicitly. The base must be at least two and at
most sixteen.

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  #8 (permalink)  
Old 07-12-2008, 06:36 AM
MikeWhy
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Default Re: What does the sharp sign mean in VHDL?

"diogratia" <[email protected]> wrote in message
news:[email protected]...
> On Jul 11, 1:13 am, Tricky <Trickyh...@gmail.com> wrote:
>> > OT2: How many examples are there of digit-strings N, M
>> > such that M /= N and N#M# = M#N# ???
>> > --

>>
>> off the top of my head:
>>
>> 10#2# = 2#10 = 2
>> 10#3# = 3#10 = 3
>> etc, forever
>> (1#10# is not a legal representation)
>>
>> also, any combination of 11-19, eg 11#19 = 19#11, 13#16#
>>
>> After this, differences gradually diverge, eg
>> 11#20# = 22, 20#11# = 21 diff = 1
>> 11#21# = 23, 21#11# = 22 diff = 1
>> ....
>> 12#20# = 24, 20#12# = 22 diff = 2
>> 12#21# = 25, 21#12# = 23 diff = 2
>> .....
>> etc
>>
>> so assuming thats all of them, then 56 + (infinity: 10#N#, N#10# where
>> N /= 0, 1 or 10)
>>

> Not in VHDL:
>
> 13.4.2 Based literals
>
> A based literal is an abstract literal expressed in a form that
> specifies the base explicitly. The base must be at least two and at
> most sixteen.


The muse posed stipulated M /= N.


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  #9 (permalink)  
Old 07-12-2008, 04:47 PM
diogratia
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Posts: n/a
Default Re: What does the sharp sign mean in VHDL?

On Jul 12, 4:36 pm, "MikeWhy" <boat042-nos...@yahoo.com> wrote:
> "diogratia" <diogra...@gmail.com> wrote in message
>
> > On Jul 11, 1:13 am, Tricky <Trickyh...@gmail.com> wrote:
> >> > OT2: How many examples are there of digit-strings N, M
> >> > such that M /= N and N#M# = M#N# ???
> >> > --

>
> > Not in VHDL:

>
> > 13.4.2 Based literals

>
> > A based literal is an abstract literal expressed in a form that
> > specifies the base explicitly. The base must be at least two and at
> > most sixteen.

>
> The muse posed stipulated M /= N.


With based literals comprised of base and based integers substituted
appropriately for N and M in the expression described by:

N#M# = M#N#
e.g.:
2#10# = 10#2#

M is limited by the right hand based literal and N is limited by the
left hand based literal by acceptable values of the base. The base in
the domain 'at least two and at most sixteen'.

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  #10 (permalink)  
Old 07-13-2008, 09:52 PM
David M. Palmer
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Posts: n/a
Default Re: What does the sharp sign mean in VHDL?

In article <[email protected]>, Jonathan
Bromley <[email protected]> wrote:

> On Thu, 10 Jul 2008 11:55:03 +0100, Brian Drummond wrote:
>
> >And, of course, 6 * 9 = 13#42#

>
> But if everything is answered, what's the point of Usenet?
>
> Seriously OT: I've known that relationship for some time,
> but I've never seen any evidence to say whether or not
> Douglas Adams did it deliberately - I had always assumed
> he was far too smart for it to be an accident, but...
> do you have any references for that?


łnobody writes jokes in base 13, I may be a pretty sad person but I
donąt write jokes in base 13.˛
-- Douglas Adams.

--
David M. Palmer [email protected] (formerly @clark.net, @ematic.com)
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