FPGA Central

Hello everybody,

I just tried a code snippet like this:


ARCHITECTURE xyz OF abc IS
BEGIN
PROCESS
BEGIN
<Some sequential statements>
WAIT on i1;
END PROCESS;
END xyz;


....where i1 is an IN-port (std_logic) in the respective entity.

Quartus II 7.0 Web Edition says:
"Wait Statement must contain condition clause with UNITL keyword."

Xilinx ISE 9.1 says:
"Bad condition in wait statement or only one clock per process."

According to my understanding and several tutorials and books the code
should work, since the "WAIT ON" at the end of the process is a valid
alternative to the sensitivity list.

Am I wrong?
Can anyone help?

Best regards
Markus

On May 31, 1:32 pm, Markus Jochim <joc...@dc.uni-due.de> wrote:
> Hello everybody,
>
> I just tried a code snippet like this:
>
> ARCHITECTURE xyz OF abc IS
> BEGIN
> PROCESS
> BEGIN
> <Some sequential statements>
> WAIT on i1;
> END PROCESS;
> END xyz;
>
> ...where i1 is an IN-port (std_logic) in the respective entity.
>
> Quartus II 7.0 Web Edition says:
> "Wait Statement must contain condition clause with UNITL keyword."
>
> Xilinx ISE 9.1 says:
> "Bad condition in wait statement or only one clock per process."
>
> According to my understanding and several tutorials and books the code
> should work, since the "WAIT ON" at the end of the process is a valid
> alternative to the sensitivity list.
>
> Am I wrong?
> Can anyone help?
>
> Best regards
> Markus

IINM, that wait statement will trigger on any event on i1, including
rising and falling edges. That is not synthesizable AFAIK.

andy

Markus,
If you look at 1076.6-2004 you will find that
this coding style is not supported for VHDL RTL
coding styles.

From a business perspective vendors have to spend
money to add and maintain features.

From a user perspective, I can already do this as
easily with a sensitivity list. I have many other
things that are much more important than this
that I need synthesis vendors to implement (that
they have not yet). If you want a list, start with
any of the coding styles that are in 1076.6-2004.
Also look on my the papers section of my website for
papers on 1076.6. http://www.synthworks.com/papers

Best Regards,
Jim


> Hello everybody,
>
> I just tried a code snippet like this:
>
>
> ARCHITECTURE xyz OF abc IS
> BEGIN
> PROCESS
> BEGIN
> <Some sequential statements>
> WAIT on i1;
> END PROCESS;
> END xyz;
>
>
> ...where i1 is an IN-port (std_logic) in the respective entity.
>
> Quartus II 7.0 Web Edition says:
> "Wait Statement must contain condition clause with UNITL keyword."
>
> Xilinx ISE 9.1 says:
> "Bad condition in wait statement or only one clock per process."
>
> According to my understanding and several tutorials and books the code
> should work, since the "WAIT ON" at the end of the process is a valid
> alternative to the sensitivity list.
>
> Am I wrong?
> Can anyone help?
>
> Best regards
> Markus
>
>

"Markus Jochim" <[email protected]> wrote in message
news:[email protected]..
> Hello everybody,
>
> I just tried a code snippet like this:
>
>
> ARCHITECTURE xyz OF abc IS
> BEGIN
> PROCESS
> BEGIN
> <Some sequential statements>
> WAIT on i1;
> END PROCESS;
> END xyz;
>
>
> ...where i1 is an IN-port (std_logic) in the respective entity.
>
> Quartus II 7.0 Web Edition says:
> "Wait Statement must contain condition clause with UNITL keyword."
>
> Xilinx ISE 9.1 says:
> "Bad condition in wait statement or only one clock per process."
>
> According to my understanding and several tutorials and books the code
> should work, since the "WAIT ON" at the end of the process is a valid
> alternative to the sensitivity list.

Hi Markus,

Most modern synthesis tools support 2 types of FF coding styles,

process (clk)
begin
if rising_edge(clk) then
..
end if;
end process;

or,

process
begin
wait until clk'event and clk = '0';
..
end process;

They also support dual edge triggering but only for those fpga that have
dual edge FF like the Xilinx Coolrunner,

Hans
www.ht-lab.com


>
> Am I wrong?
> Can anyone help?
>
> Best regards
> Markus
>
>