FPGA Central

VHDL gurus,

I am designing an FPGA using VHDL and I ran into a little problem.

My top level file is mytop.vhd and I instantiate numerous components.
One of the components is mycomp.vhd. A signal my_sig(15 downto 0) is
declared in the component architecture. However, this signal is not
part of the port map. How do I access this signal(s) in my top level
file? Does VHDL even support this?

One way of working around this problem is to list the signal in the
port map. However, this component is instantiated numerous times in my
top level file and I don?t need this signal for each instance.

I tried looking up references on the web but couldn?t find any useful
information. I would really appreciate if someone can suggest a
solution.

Thanks
Naveen.

Naveen R <[email protected]> wrote:
> One way of working around this problem is to list the signal in the
> port map. However, this component is instantiated numerous times in my
> top level file and I don?t need this signal for each instance.

Thats no problem in general, you can leave the signal in the
port map open if you dont need it in all instantiated components.
i.e.:

inst_1_mycomp : mycomp port map (
my_sig => top_level_of_my_sig_from_inst_1,
[...]
);

inst_2_mycomp : mycomp port map (
my_sig => open,
[...]
);

WD
--

Hi,

Add this signal to the port list.
You can simply skip it in the instantiation if you assign a value to
this port in component declaration.
component mycomp is
port (
....
my_sig : in std_logic_vector(15 downto 0) := (others => '0');
....
This implies also mapping by name in your instantiation.

If you need it to be an output you can always use 'open',

u0 : mycomp
port map (
.....
my_sig => open,
.....
)

Finally, if you really want to leave it as internal signal usually the
'force' command allows you to drive the signals not only from the top
level.

Marcin

[email protected] (Naveen R) wrote in message news:<[email protected] com>...
> VHDL gurus,
>
> I am designing an FPGA using VHDL and I ran into a little problem.
>
> My top level file is mytop.vhd and I instantiate numerous components.
> One of the components is mycomp.vhd. A signal my_sig(15 downto 0) is
> declared in the component architecture. However, this signal is not
> part of the port map. How do I access this signal(s) in my top level
> file? Does VHDL even support this?
>
> One way of working around this problem is to list the signal in the
> port map. However, this component is instantiated numerous times in my
> top level file and I don?t need this signal for each instance.
>
> I tried looking up references on the web but couldn?t find any useful
> information. I would really appreciate if someone can suggest a
> solution.
>
> Thanks
> Naveen.

Naveen R wrote:
>
> VHDL gurus,
>
> I am designing an FPGA using VHDL and I ran into a little problem.
>
> My top level file is mytop.vhd and I instantiate numerous components.
> One of the components is mycomp.vhd. A signal my_sig(15 downto 0) is
> declared in the component architecture. However, this signal is not
> part of the port map. How do I access this signal(s) in my top level
> file? Does VHDL even support this?

Not as part of the language. However, most simulators will allow you to
look at a signal anywhere in the hierarchy.

> One way of working around this problem is to list the signal in the
> port map. However, this component is instantiated numerous times in my
> top level file and I don?t need this signal for each instance.
>
> I tried looking up references on the web but couldn?t find any useful
> information. I would really appreciate if someone can suggest a
> solution.

You can define a signal in a package and include the package in both
your top-level and the file(s) you want to be able to look at. You can
then have access to the signals in any file where the package is
included, without using the port list.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

Hello,
Just to mention that i tried ones the use of the global signals in a
package and it worked well in the simulation. The problem that you could
face will be with synthesis tools that don't implement yet all the VHDL
specification. May be some EDA like Synopsys or Cadence will do that but
for Synplify and Leonardo Spectrum it will not.
You'd better use your signal as a port and let it open if it's an output.
Good luck

[email protected] wrote:
>
> Hello,
> Just to mention that i tried ones the use of the global signals in a
> package and it worked well in the simulation. The problem that you could
> face will be with synthesis tools that don't implement yet all the VHDL
> specification. May be some EDA like Synopsys or Cadence will do that but
> for Synplify and Leonardo Spectrum it will not.
> You'd better use your signal as a port and let it open if it's an output.
> Good luck

I beg to differ . . . The current version of Synplify DOES support
synthesis of global signals because I've used this feature to bring a
debug port to my top level. I believe it worked in Xilinx XST as well
but I don't trust my memory and I can't say for sure. You might need to
do a top-down synthesis for it to work but I'm just guessing.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

Hi tim,
I tried to syntesis a simple code using global signals withe synplify 7.3.3
pro at the lab. Same as for the 7.2 pro vesion that i tried before. This is
my example:
--the package
library ieee;
use ieee.std_logic_1164.all;
package my_package is
signal Q: std_logic; -- Global signal
end my_package;

--the entity
library ieee;
use ieee.std_logic_1164.all;
entity testg is
port (clk: in std_logic;
ins : in std_logic;
outs: out std_logic );
end testg;
architecture arch of testg is
--signal Q: std_logic;
begin
process(clk)
begin
if clk'event and clk='1' then
work.my_package.Q<=ins;
outs<=work.my_package.Q;
--Q<=ins;
--Outs<=Q;
end if;
end process;
end;
================================================== ===========
it give
Synplicity VHDL Compiler, version Compilers 7.3, Build 036R, built Oct 1
2003
Copyright (C) 1994-2002, Synplicity Inc. All Rights Reserved

@N:"C:\My_Designs\tes.vhd":5:7:5:11|Top entity is set to testg.
VHDL syntax check successful!
Synthesizing work.testg.arch
@E:Internal Error
Please call Synplicity Support (USA) at (408) 215-6000 or send
email including this log and test case to [email protected]
================================================== ==========

I'll try some other tools latter. Do u have any suggestion???
yours

[email protected] wrote:
>
> Hi tim,
> I tried to syntesis a simple code using global signals withe synplify 7.3.3
> pro at the lab. Same as for the 7.2 pro vesion that i tried before. This is
> my example:
> --the package
> library ieee;
> use ieee.std_logic_1164.all;
> package my_package is
> signal Q: std_logic; -- Global signal
> end my_package;
>
> --the entity
> library ieee;
> use ieee.std_logic_1164.all;
> entity testg is
> port (clk: in std_logic;
> ins : in std_logic;
> outs: out std_logic );
> end testg;
> architecture arch of testg is
> --signal Q: std_logic;
> begin
> process(clk)
> begin
> if clk'event and clk='1' then
> work.my_package.Q<=ins;
> outs<=work.my_package.Q;
> --Q<=ins;
> --Outs<=Q;
> end if;
> end process;
> end;
> ================================================== ===========
> it give
> Synplicity VHDL Compiler, version Compilers 7.3, Build 036R, built Oct 1
> 2003
> Copyright (C) 1994-2002, Synplicity Inc. All Rights Reserved
>
> @N:"C:\My_Designs\tes.vhd":5:7:5:11|Top entity is set to testg.
> VHDL syntax check successful!

This line suggests that Synplify is actually happy with the code but . .
..

> Synthesizing work.testg.arch
> @E:Internal Error

.. . . then blows up due to a bug.

> Please call Synplicity Support (USA) at (408) 215-6000 or send
> email including this log and test case to [email protected]
> ================================================== ==========

What you have here is a Synplify bug causing the synthesis to crash.
This doesn't mean that global signals don't work in general. I suggest
you do as it says and report the bug to Synplicity.

I did something different: I defined a global signal and assigned to it
( global_signal <= stuff; ) in a sub-module and then drove the data out
at the top level ( debug_out_pin <= global_signal; ). I ran it all the
way through the Synplicity and Xilinx tools and it appeared to work. I
haven't done anything further as I'm only now starting the coding for
the project (months of spec writing finally over, Yeah!!).
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

[email protected] wrote:
> Synplicity VHDL Compiler, version Compilers 7.3, Build 036R, built Oct 1
> 2003
> @E:Internal Error

Your example crashed

Synplicity VHDL Compiler, version Compilers 7.3, Build 055R, built Oct 27 2003

too. Maybe this a bug in synplify.


And your example with xilinx XST produce:

Release 5.2.03i - xst F.31
[...]
Analyzing Entity <testg> (Architecture <arch>).
ERROR:Xst:839 - /tmp/junk/test.vhd line 24: Signal is not defined : 'q'.
24: work.my_package.Q<=ins;


WD
--