FPGA Central

Does there exists a software tool that parses a VHDL design project
and generates a graphical view of the entity hierarchy? For
documentation purposes. It should preferably be presented in a tree
structure.

Thanks,

Stein Kjolstad

Stein Kjølstad wrote:
>
> Does there exists a software tool that parses a VHDL design project
> and generates a graphical view of the entity hierarchy? For
> documentation purposes. It should preferably be presented in a tree
> structure.

ChipVault, http://chipvault.sourceforge.net/ , will do it although you
might find the interface is a bit "klunky".
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

Stein Kjølstad wrote:

> Does there exists a software tool that parses a VHDL design project
> and generates a graphical view of the entity hierarchy? For
> documentation purposes. It should preferably be presented in a tree
> structure.
>
> Thanks,
>
> Stein Kjolstad

HDS designer will do this work greatly (The result is a little bit
depending on how is written the VHDL). Works well!

If you want to see a result, let me know. If you send me your VHDL, I
can do a graphical view of you VHDL in the minute.

And the result can be edited in your favorite HTML browser!

Larry
www.amontec.com