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hello:
I am a beginner of vhdl, I have some knowledge about verilog. please
help me with this problem:
In VHDL serveral vector can concatenate like " a & b & c " also (a ,b
,). i know this can be used as the right operand when assigning. but can
the concatenated vector be the left operand? i writed like this
(a,b,c)<= d ; or
a & & c <= d;
but all can not pass the compilation.

can tell me how the cooncatenated vector be the left operand? thanks
you!!

"pandora" <[email protected]> wrote in message
news:[email protected] lkaboutprogramming.com...
> hello:
> I am a beginner of vhdl, I have some knowledge about verilog. please
> help me with this problem:
> In VHDL serveral vector can concatenate like " a & b & c " also (a ,b
> ,). i know this can be used as the right operand when assigning. but can
> the concatenated vector be the left operand? i writed like this
> (a,b,c)<= d ; or
> a & & c <= d;
> but all can not pass the compilation.
>
> can tell me how the cooncatenated vector be the left operand? thanks
> you!!
>
I've not checked, but I don't think you can do this; you have to slice the
rhs thus:

a <= d(msb downto X);
b <= d(X-1 downto Y);
c <= d(Y-1 downto 0);

Or something similar.

Niv.

"pandora" <[email protected]> wrote in message
news:[email protected] lkaboutprogramming.com...
> hello:
> I am a beginner of vhdl, I have some knowledge about verilog. please
> help me with this problem:
> In VHDL serveral vector can concatenate like " a & b & c " also (a ,b
> ,). i know this can be used as the right operand when assigning. but can
> the concatenated vector be the left operand? i writed like this
> (a,b,c)<= d ; or
> a & & c <= d;
> but all can not pass the compilation.
>
> can tell me how the cooncatenated vector be the left operand? thanks
> you!!

Here an example. It would be nice if the line marked with --***
could be (co,s)<=...
But that is not allowed (yet).

Egbert Molenkamp

LIBRARY ieee;
USE ieee.numeric_bit.ALL;
ENTITY adder IS
PORT (a,b : IN unsigned(1 DOWNTO 0);
ci : IN bit;
s : OUT unsigned(1 DOWNTO 0);
co : OUT bit);
END adder;
ARCHITECTURE demo OF adder IS
BEGIN
(co,s(1),s(0)) <= ('0'&a) + b + ('0'&ci) ; --***
END demo;

but sometimes the left part is an expression, you can not write like this!
so it is really troublesome to write every bit in the left when it is a
very long vector.

pandora wrote:

> (a,b,c)<= d ; or
> a & & c <= d;
> but all can not pass the compilation.

http://groups.google.com/groups?q=vh...+qualification

-- Mike Treseler

"pandora" <[email protected]> wrote
> but sometimes the left part is an expression, you can not write like this!
> so it is really troublesome to write every bit in the left when it is a
> very long vector.

Then use a variable

my_var:=my_function(x,y,z);
a<=my_var(t downto s);
b<=my_var(s-1 downto r);
c<=my_var(r-1 downto 0);

bye Thomas