FPGA Central

Hi all,
Can anyone check whether my VHDL code for variable step for-loop is
correct or not??? Many thanks!!!

------- C code example --------
int ip1;
for (ip1=1; ip1<=10; ip1+=2) {
....
}

------- VHDL code example -------
varible ip1 : integer;
for ip1 in 1 to 10 loop
ip1:=ip1+2;
....
end loop;

Stanley

"cltsaig" <[email protected]> wrote in message
news:[email protected] lkaboutprogramming.com...
> Hi all,
> Can anyone check whether my VHDL code for variable step for-loop is
> correct or not??? Many thanks!!!
>
> ------- C code example --------
> int ip1;
> for (ip1=1; ip1<=10; ip1+=2) {
> ...
> }
>
> ------- VHDL code example -------
> varible ip1 : integer;
> for ip1 in 1 to 10 loop
> ip1:=ip1+2;
> ...
> end loop;
>
> Stanley
>

No it won't work. You can't assign to the loop parameter
in VHDL as it is a constant - VHDL effectively unrolls the loop
creating copies, and for each copy ip1 is a constant.

Also you don't have to declare the loop parameter ip1 - in
fact if you do, the loop parameter ip1 hides (makes invisible)
the variable ip1 - they are two different objects in VHDL!

Hence you need a separate variable to hold the doubled
index, e.g.

variable ip2 : natural range 0 to 10;

ip2 := 0;
for ip1 in 1 to 5 loop -- ip1 is implicitly declared
ip2 := ip2 + 2;
.... -- use ip2 in the indexing of course!
end loop;

regards

Alan

--
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223 mail:
[email protected]
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.

Stanley,
> Hi all,
> Can anyone check whether my VHDL code for variable step for-loop is
> correct or not??? Many thanks!!!
>
> ------- C code example --------
> int ip1;
> for (ip1=1; ip1<=10; ip1+=2) {
> ...
> }
>
> ------- VHDL code example -------
> varible ip1 : integer;
> for ip1 in 1 to 10 loop
> ip1:=ip1+2;
> ...
> end loop;
>

You can use a for loop to control the number of
iternations only. Hence one way to translate your
"C" code is:

variable ip1 : integer ;

for loop_var in 0 to 4 loop -- don't declare loop_var
ip1 := (loop_var * 2) + 1 ;
. . .

end loop;


Another way is to unroll the C code into its
equivalent while loop:

variable ip1 : integer ;

ip1 := 1 ;
while ip1 <= 10 loop
. . .

ip1 := ip1+2 ;
end loop ;


Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

Hi Alan and Jim,
Greatly thanks from your feedback...I kinda perceived the error that I
made on my previous post.

Although, I had an another enigma need you expert/guru's feedback? The
concern is how to reproduce this C function into VHDL?? Is it feasible??
I'd declared a package that defines an floating point array.

void fun(float data[], int nn[], int ndim, int sign)
{
.....
}

------- VHDL code --------------------------------
package pack1 is
type array_fp32 is array (positive range <>) of fp32;
end pack1;

use work.pack1.all;
entity fun is
port(
data: in array_fp32 ;
nn: in array_integer;
ndim: in integer;
sign: in integer;
clk:in std_logic;
rst:in std_logic;
resultut array_fp32
);
end fun;


Kindest regards,
Stanley

"cltsaig" <[email protected]> wrote in message
news:[email protected] lkaboutprogramming.com...
> Hi Alan and Jim,
> Greatly thanks from your feedback...I kinda perceived the error that
I
> made on my previous post.
>
> Although, I had an another enigma need you expert/guru's feedback?
The
> concern is how to reproduce this C function into VHDL?? Is it
feasible??
> I'd declared a package that defines an floating point array.
>
> void fun(float data[], int nn[], int ndim, int sign)
> {
> ....
> }
>
> ------- VHDL code --------------------------------
> package pack1 is
> type array_fp32 is array (positive range <>) of fp32;
> end pack1;
>
> use work.pack1.all;
> entity fun is
> port(
> data: in array_fp32 ;
> nn: in array_integer;
> ndim: in integer;
> sign: in integer;
> clk:in std_logic;
> rst:in std_logic;
> resultut array_fp32
> );
> end fun;
>
>

This should work fine, as long as you have also defined
the array_integer type somwehere.

You can have entities with unconstrained ports, though
not all synthesis tools are happy with them (assuming
of course that you instantatiate a componenent and
bind the ports so that the actual widths are known).

Alternatively you can write a procedure corresponding
to your function. Procedures with unconstrained ports
normally are fine with synthesis tools, if they result
in combinational logic. If they have a clock (as yours
seems to) then some synthesis tools don't like them.

Of course if you're not going to synthesise the code,
don't worry if it's synthesisable or not :-)

regards

Alan

--
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223 mail:
[email protected]
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.