FPGA Central

Hi there

I have defined

signal xx std_logic_vector(2 downto 0);
signal zz unsigned(4 downto 0);

and I want to assign

zz <= unsigned(xx);

without getting an array type mismatch and without doing

zz <= unsigned ("00" & xx);

which works fine but is not very portable and flexible.

Is there a way to 'extend' xx with a ieee library function?

maybe it is trivial, but I cannot get rid of that I am so tired, it is
so late now in Italy now ...

Thanks to who'll reply

Try

libray ieee;
use ieee.std_logic_arith.all;

....

zz <= conv_unsigned(xx,zz'length);

"andy" <[email protected]> ha scritto nel messaggio
news:[email protected] om...
> Hi there
>
> I have defined
>
> signal xx std_logic_vector(2 downto 0);
> signal zz unsigned(4 downto 0);
>
> and I want to assign
>
> zz <= unsigned(xx);
>
> without getting an array type mismatch and without doing
>
> zz <= unsigned ("00" & xx);
>
> which works fine but is not very portable and flexible.
>
> Is there a way to 'extend' xx with a ieee library function?
>
> maybe it is trivial, but I cannot get rid of that I am so tired, it is
> so late now in Italy now ...
>
> Thanks to who'll reply

http://groups.google.com/groups?q=vh...ed+numeric_std

-- Mike Treseler