FPGA Central

Hi again ,

I'm having a few problems with mapping my VHDL program. It gives me a
couple of Maplib:661 error. For example:

LUT4 symbol "TxD_start_mux00031" (output signal=TxD_start)
has input signal "TxD_start_cmp_lt0000" which will be trimmed. See
the trim
report for details about why the input signal will become undriven.

The mapreport says: The signal "TxD_start_cmp_lt0000" is unused and
has been removed.


I mean, what gives??? The mapper removed a signal thinking it's not
used, and later it gives an error because he needs it but has been
trimmed?


The logical solution would be to turn the trimming of unused signals
off. I did that (unchecked it) but it doesn't make a difference!! Is
this a bug or some sort?

I'm using Xilinx 9.1i for the record.

Thx
Jonas

[email protected] wrote:

> The logical solution would be to turn the trimming of unused signals
> off. I did that (unchecked it) but it doesn't make a difference!! Is
> this a bug or some sort?

Probably not. Maybe that signal does not affect
any output port. Synthesis is correct to trim
in that case. I use simulation to verify
incomplete designs. Good luck.

-- Mike Treseler

On 11 okt, 18:11, Mike Treseler <mike_trese...@comcast.net> wrote:
> jonasm...@gmail.com wrote:
> > The logical solution would be to turn the trimming of unused signals
> > off. I did that (unchecked it) but it doesn't make a difference!! Is
> > this a bug or some sort?
>
> Probably not. Maybe that signal does not affect
> any output port. Synthesis is correct to trim
> in that case. I use simulation to verify
> incomplete designs. Good luck.
>
> -- Mike Treseler


hmm,

fixed it, but i really don't understand why