FPGA Central

Hi everyone,

I've got some simple code, shown below:
entity hello_world is -- test bench (top level like "main")
end entity hello_world;

library IEEE; -- but may need other libraries
use IEEE.std_logic_1164.all; -- basic logic types
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library STD;
use STD.textio.all; -- basic I/O

architecture test of hello_world is -- where declarations are placed
begin
my_print : process is -- a process is parallel
variable my_line : line; -- type 'line' comes from
textio
begin

wait;
end process my_print;
end architecture test;

Xilinx complains that

"ERROR:HDLParsers:3312 - C:/Xilinx/projects/test/test_io.vhd Line 21.
Undefined symbol 'line'."

I had a look at the Xilinx XST User Guide, and page 284 clearly shows
that 'line' is a supported type! I read a couple of other posts, and
they suggested that I enclose the code with -- pragma translate_off /
-- pragma translate_on, but Xilinx complained that:

"ERROR:HDLParsers:164 - C:/Xilinx/projects/test/test_io.vhd Line 27.
parse error, unexpected $"

What's going on??

Regards

Taras

Taras_96 wrote:
> Hi everyone,
>
> I've got some simple code, shown below:
> entity hello_world is -- test bench (top level like "main")
> end entity hello_world;
>
> library IEEE; -- but may need other libraries
> use IEEE.std_logic_1164.all; -- basic logic types
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
> Library STD;
> use STD.textio.all; -- basic I/O
>
> architecture test of hello_world is -- where declarations are placed
> begin
> my_print : process is -- a process is parallel
> variable my_line : line; -- type 'line' comes from
> textio
> begin
>
> wait;
> end process my_print;
> end architecture test;
>
> Xilinx complains that
>
> "ERROR:HDLParsers:3312 - C:/Xilinx/projects/test/test_io.vhd Line 21.
> Undefined symbol 'line'."
>
> I had a look at the Xilinx XST User Guide, and page 284 clearly shows
> that 'line' is a supported type! I read a couple of other posts, and
> they suggested that I enclose the code with -- pragma translate_off /
> -- pragma translate_on, but Xilinx complained that:
>
> "ERROR:HDLParsers:164 - C:/Xilinx/projects/test/test_io.vhd Line 27.
> parse error, unexpected $"
>
> What's going on??
>


Do you want to _synthesize_ writeline and access types (line) ?
Where do you expect the text to go to in the silicon ?

Files are for simulation (ModelSim), not for silicon (XST).

you may find useful to use file output in synthesizable code
for debug purpose, in which case you should embed this code within
the correct pragmas (in doubt, use synopsys' which are usually recognized).

Bert Cuzeau

Thanks Bert,

I was getting confused about what Xilinx has to offer. I was using
'Check Syntax' to check unsynthesisable code, expecting it to check to
make sure it was correct VHDL, but it must actually check to see if its
synthesisable as well. Why doesn't Xilinx support writing files?

Thanks

Taras

Taras_96 wrote:
> Thanks Bert,
>
> I was getting confused about what Xilinx has to offer. I was using
> 'Check Syntax' to check unsynthesisable code, expecting it to check
to
> make sure it was correct VHDL, but it must actually check to see if
its
> synthesisable as well. Why doesn't Xilinx support writing files?

The question was already answered: how is the synthesis tool supposed
to know how to put file I/O into a chip? It can't! File I/O is for
simulation use only. Remember that synthesis supports only a small
subset of the language -- a not-so-minor detail that the XST
documentation makes clear.

Another question: why are you using:

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

I thought these were deprecated in favor of numeric_std.

--a

I was getting confused by the difference between Xilinx and Modelsim.
I was thinking (for some reason) that Modelsim is a subset of Xilinx,
which isn't true. In my last message I was asking why it wasn't
possible to write files for simulation purposes only, thinking that
because Modelsim was a subset of Xilinx, it should be able to simulate.


I was using those libraries because they were the first ones to pop up
in Andrew Rushton's book - I think I might change to numeric_std...

Thanks

Taras

hey dude, where do you come from, carelessly dabbling with free tools
without trying to know what its about.
Please dont assume that everything that runs though a software is a
software program.