FPGA Central

Hi,

I've got the following error:
parse error, unexpected WHEN, expecting SEMICOLON

on synthesis of the this peace of code:

entity trigger is
port(
clk : in std_logic;
...
);
end entity;

architecture behavioral of trigger is

signal m_pattern : std_logic := '0';
signal m_edge : std_logic := '0';

begin

...

trig_proc: process(clk)
begin
if rising_edge(clk) then
match <= '1' -- HERE
when (m_pattern ='1') and (m_edge = '1')
else '0';
end if;

end process;

end behavioral;

Is this not allowed inside a process, only inside archtitectures??

Thanks and regards,
Olaf

Olaf Petzold wrote:


> if rising_edge(clk) then
> match <= '1' -- HERE
> when (m_pattern ='1') and (m_edge = '1')
> else '0';
> end if;

> Is this not allowed inside a process, only inside archtitectures??

Use *if/then/else* inside a process.
Use *when* outside.
That's just the way it is.

-- Mike Treseler