FPGA Central

Hi guys,

I'm trying to use the asynchronous input synchronization template from
ISE 10.1, but I get a double warning I do not understand:

WARNING:ConstraintSystem:119 - Constraint <NET: UniqueName:
/SigGenTop/EXPANDED/S0\/sreg<1> HBLKNM = "sync_reg">: This constraint
cannot
be distributed from the design objects matching 'NET: UniqueName:
/SigGenTop/EXPANDED/S0\/sreg<1>' because those design objects do not
contain
or drive any instances of the correct type.

WARNING:ConstraintSystem:119 - Constraint <NET: UniqueName:
/SigGenTop/EXPANDED/S0\/sreg<0> HBLKNM = "sync_reg">: This constraint
cannot
be distributed from the design objects matching 'NET: UniqueName:
/SigGenTop/EXPANDED/S0\/sreg<0>' because those design objects do not
contain
or drive any instances of the correct type.

Anybody can explain what this means, and how I can avoid it?

-------------
Synchronizer:
-------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity syncronizer is
Port ( clk : in std_logic;
async_in : in STD_LOGIC;
sync_out : out STD_LOGIC);
end syncronizer;

architecture Behavioral of syncronizer is

signal sreg : std_logic_vector(1 downto 0);

attribute TIG : string;
attribute IOB : string;
attribute ASYNC_REG : string;
attribute SHIFT_EXTRACT : string;
attribute HBLKNM : string;

attribute TIG of async_in : signal is "TRUE";
attribute IOB of async_in : signal is "FALSE";
attribute ASYNC_REG of sreg : signal is "TRUE";
attribute SHIFT_EXTRACT of sreg : signal is "NO";
attribute HBLKNM of sreg : signal is "sync_reg";

begin

process (clk)
begin
if clk'event and clk='1' then
sync_out <= sreg(1);
sreg <= sreg(0) & async_in;
end if;
end process;

end Behavioral;

--------------
Instantiation:
--------------

S0: entity WORK.syncronizer
port map(Clk=> MClk, async_in => SS, sync_out => synchedSS);

//michael

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Not sure if this is related, but sreg(1) should not be considered an
asynchronous register, only sreg(0). You may have to split them up
into separate signals to handle it. You will also want to make sure
(constrain) that sreg(0) does not get replicated for fanout (e.g. if
sreg(1) gets replicated enough due to high fanout, that can ripple to
replicating sreg(0).)

Is the output from your syncrhonizer going anywhere? If not it may be
getting optimized away, thus prompting the warnings.

Andy

On Thu, 09 Jul 2009 15:54:47 +0200, Andy <jonesandy@comcast.net> wrote:

> Not sure if this is related, but sreg(1) should not be considered an
> asynchronous register, only sreg(0). You may have to split them up
> into separate signals to handle it.

Ok, I will look at that.

> You will also want to make sure (constrain) that sreg(0) does not get
> replicated for fanout (e.g. if sreg(1) gets replicated enough due tohigh
> fanout, that can ripple to replicating sreg(0).)

It doesn't look like it is getting replicated (and it shouldn't unless
I had made a mistake).

> Is the output from your syncrhonizer going anywhere? If not it may be
> getting optimized away, thus prompting the warnings.

Yes, it is being used (SPI-slave), and it works, but still I would like
to know the meaning and consequences of this warning.

//michael

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