FPGA Central

Hi,

I have problems using both std.textio.all and ieee.std_logic_textio.all
When I try to compile ModelSim gives me an error: Subprogram 'write' is
ambiguous. Suitable definitions exist in packages 'std_logic_textio' and
'textio'.

When i take a look at source code for std_logic_textio it says:
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.

This is exactly what I want it to do. Any tips how to make this happen?

Magne Munkejord wrote:
> Hi,
>
> I have problems using both std.textio.all and ieee.std_logic_textio.all
> When I try to compile ModelSim gives me an error: Subprogram 'write' is
> ambiguous. Suitable definitions exist in packages 'std_logic_textio' and
> 'textio'.
>
> When i take a look at source code for std_logic_textio it says:
> -- Purpose: This package overloads the standard TEXTIO procedures
> -- READ and WRITE.
>
> This is exactly what I want it to do. Any tips how to make this happen?

I found a solution:
write(my_line, string'("my_string");
instead of:
write(my_line, "my_string");

(my_line is type LINE as defined in std.textio)