FPGA Central

Hi,

I decode a command opcode on upper byte and the target id on lower byte
of the command like this:

architecture behavioral of marshall is

procedure set_signal (
variable id : in std_ulogic_vector(7 downto 0);
signal sig : out std_ulogic;
constant value : in std_ulogic) is
variable n : integer range 1 to 8;
begin
n := to_integer(unsigned(id));
sig(n) <= value; -- XXX
end procedure;

begin

decode: process (clk, command, reset) is
variable cmd_ub : std_ulogic_vector(7 downto 0); -- upper byte
variable cmd_lb : std_ulogic_vector(7 downto 0); -- lower byte
begin
cmd_ub := command(15 downto 8); -- operation
cmd_lb := command(7 downto 0); -- target

if (reset = RESET_ACTIVE) then
...
elsif rising_edge(clk) then
case cmd_ub is
...
when x"C0" => set_signal(cmd_lb, set_bit_value, '1');
when x"C1" => set_signal(cmd_lb, set_bit_mask, '1');
...
when others => null;
end case;
end if;
end process;
...

Unfortunately I get an error: "Prefix of indexed name must be an array"
at the assigning line: sig(n) <= value;
Isn't it an array?? Where is my mistake and how to fix it? By using this
procedure I want to omit the nested case switches.

Thanks a lot again
Olaf

On Thu, 03 May 2007 21:38:50 +0200, Olaf <[email protected]> wrote:

>Hi,
>
>I decode a command opcode on upper byte and the target id on lower byte
>of the command like this:
>
>architecture behavioral of marshall is
>
> procedure set_signal (
> variable id : in std_ulogic_vector(7 downto 0);
> signal sig : out std_ulogic;
> constant value : in std_ulogic) is
> variable n : integer range 1 to 8;
> begin
> n := to_integer(unsigned(id));
> sig(n) <= value; -- XXX
> end procedure;
>
>begin
>
> decode: process (clk, command, reset) is
> variable cmd_ub : std_ulogic_vector(7 downto 0); -- upper byte
> variable cmd_lb : std_ulogic_vector(7 downto 0); -- lower byte
> begin
> cmd_ub := command(15 downto 8); -- operation
> cmd_lb := command(7 downto 0); -- target
>
> if (reset = RESET_ACTIVE) then
> ...
> elsif rising_edge(clk) then
> case cmd_ub is
> ...
> when x"C0" => set_signal(cmd_lb, set_bit_value, '1');
> when x"C1" => set_signal(cmd_lb, set_bit_mask, '1');
> ...
> when others => null;
> end case;
> end if;
> end process;
> ...
>
>Unfortunately I get an error: "Prefix of indexed name must be an array"
>at the assigning line: sig(n) <= value;
>Isn't it an array??

No, it's a std_ulogic (in the procedure header). Maybe you meant it
to be a std_ulogic_vector?

But in any case I'm quite confused. 'id' can take values in the
range 0 to 255, but you're somehow assuming that it's in the range
1 to 8. And then you're using that number to index into a vector
that seems to be indexed from 0 to 7. It may well be that there
is hidden knowledge in this design that I can't see, but right
now it looks very fragile to me.

Other oddities:
- your clocked process template is strange; not all synthesis tools
will buy it. Why do you need "command" in the sensitivity list?
Why are the variable assignments outside the clocked logic?
- What kind of beast are the signals 'set_bit_value', 'set_bit_mask'?

More clues requested :-)
--
Jonathan Bromley, Consultant

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>> Unfortunately I get an error: "Prefix of indexed name must be an array"
>> at the assigning line: sig(n) <= value;
>> Isn't it an array??
>
> No, it's a std_ulogic (in the procedure header). Maybe you meant it
> to be a std_ulogic_vector?

Yes, I mean this - obviously it was to late in the evening yesterday.
Maybe there is an unconstrained way? I start to use attributes more than
before, so I'm learning to use it slowly. Same to switch from std_logic
to std_ulogic, which seems to be the preferred way.

> But in any case I'm quite confused. 'id' can take values in the
> range 0 to 255, but you're somehow assuming that it's in the range
> 1 to 8. And then you're using that number to index into a vector

Yes, id is a vector of 8 bits width, where only a slice is used. Maybe I
should call these function width this slice, isn't?

> that seems to be indexed from 0 to 7. It may well be that there
> is hidden knowledge in this design that I can't see, but right
> now it looks very fragile to me.

any improvements to make it more robust / non-ambiguous?

> Other oddities:
> - your clocked process template is strange; not all synthesis tools
> will buy it. Why do you need "command" in the sensitivity list?
> Why are the variable assignments outside the clocked logic?

emacs's vhdl-mode did it, vcom doesn't complain it (or vcom nedded it, I
can't remember and haven't modelsim at hand at moment).

> - What kind of beast are the signals 'set_bit_value', 'set_bit_mask'?

entity out by type std_ulogic, these are encoded signals to enforce some
actions outside this entity.

> More clues requested :-)

Thanks for your answer,
Olaf