FPGA Central

Hi,

Not really an (v)HDL specific question, but hopefully there is someone
who can suggest a starting point.

I need to (digitally) generate a lock detect signal for a PLL.

Where do I start?

I assume I would count edges at both the O/P and reference clock and
then compare the two count values. This leads to a couple of
questions.
- I want the counts to be the same when the PLL is locked. Therefore I
need to restart the counts together
- The counts should be the same for N clock cycles before lock becomes
active, but we should loose lock when the counts become different.

Any suggestions or pointers greatly appreciated.

Thanks,

Steven

On 25 Sep., 19:59, moo...@yahoo.co.uk wrote:
> Hi,
>
> Not really an (v)HDL specific question, but hopefully there is someone
> who can suggest a starting point.
>
> I need to (digitally) generate a lock detect signal for a PLL.
>
> Where do I start?
>
> I assume I would count edges at both the O/P and reference clock and
> then compare the two count values. This leads to a couple of
> questions.
> - I want the counts to be the same when the PLL is locked. Therefore I
> need to restart the counts together
> - The counts should be the same for N clock cycles before lock becomes
> active, but we should loose lock when the counts become different.
>
> Any suggestions or pointers greatly appreciated.
>
> Thanks,
>
> Steven

Is it an FPGA internal PLL or an external ?

Rgds
Andre

On 27 Sep, 16:33, "ALu...@web.de" <ALu...@web.de> wrote:
> On 25 Sep., 19:59, moo...@yahoo.co.uk wrote:
>
>
>
> > Hi,
>
> > Not really an (v)HDL specific question, but hopefully there is someone
> > who can suggest a starting point.
>
> > I need to (digitally) generate a lock detect signal for a PLL.
>
> > Where do I start?
>
> > I assume I would count edges at both the O/P and reference clock and
> > then compare the two count values. This leads to a couple of
> > questions.
> > - I want the counts to be the same when the PLL is locked. Therefore I
> > need to restart the counts together
> > - The counts should be the same for N clock cycles before lock becomes
> > active, but we should loose lock when the counts become different.
>
> > Any suggestions or pointers greatly appreciated.
>
> > Thanks,
>
> > Steven
>
> Is it an FPGA internal PLL or an external ?
>
> Rgds
> Andre

It's not an FPGA, it's an ASIC.

Thanks,

Steven

On Fri, 28 Sep 2007 03:27:44 -0700, [email protected] wrote:

>> > Not really an (v)HDL specific question, but hopefully there is someone
>> > who can suggest a starting point.
>>
>> > I need to (digitally) generate a lock detect signal for a PLL.
>>
>> > Where do I start?
>>
>> > I assume I would count edges at both the O/P and reference clock and
>> > then compare the two count values. This leads to a couple of
>> > questions.
>> > - I want the counts to be the same when the PLL is locked. Therefore I
>> > need to restart the counts together
>> > - The counts should be the same for N clock cycles before lock becomes
>> > active, but we should loose lock when the counts become different.

[...]

>It's not an FPGA, it's an ASIC.

For a PLL to be in lock, you need at least the following to
be true:
- the rate of change of phase-error (i.e. the frequency slip)
should be very close to zero
- the phase error should be very close to zero
- these two conditions should be stable, i.e. they should
have persisted continuously for the last so long

If it's a reasonably high-speed analog PLL then the first two
values can presumably be extracted analog fashion, and the third
criterion is easy with a simple digital filter.

If it's a purely digital PLL (as used, for example, in recovery
of slow serial data streams) then I would imagine that the
necessary error values are explicit somewhere in the DPLL itself.

If you're trying to do all this from outside the PLL, with no
knowledge of its internals, then (a) shoot the PLL designer for
not providing an in-lock output, (b) pretty much as you suggest:
start two counters at zero, use one of the two clocks to count
each, and then wait for one of them to overflow around to zero;
at that moment, the value of the second counter (treated as
a signed 2s complement number) is proportional to the
average frequency slip. That's a crummy way to detect PLL
lock, though, because it integrates the frequency over
such a long time.

Or have I completely missed the point?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

On 28 Sep, 12:39, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Fri, 28 Sep 2007 03:27:44 -0700, moo...@yahoo.co.uk wrote:
> >> > Not really an (v)HDL specific question, but hopefully there is someone
> >> > who can suggest a starting point.
>
> >> > I need to (digitally) generate a lock detect signal for a PLL.
>
SNIP
>
> If you're trying to do all this from outside the PLL, with no
> knowledge of its internals, then (a) shoot the PLL designer for
> not providing an in-lock output, (b) pretty much as you suggest:
> start two counters at zero, use one of the two clocks to count
> each, and then wait for one of them to overflow around to zero;
> at that moment, the value of the second counter (treated as
> a signed 2s complement number) is proportional to the
> average frequency slip. That's a crummy way to detect PLL
> lock, though, because it integrates the frequency over
> such a long time.
>
> Or have I completely missed the point?
> --

Hi Jonathan,

You haven't missed the point, and your suggestion pretty much sums up
my thoughts.

Unfortunately, shooting the PLL designer is not an option ;-)

Thanks for the feedback,

Steven