FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > VHDL

VHDL comp.lang.vhdl newsgroup / Usenet

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 01-20-2007, 05:13 PM
Klawy
Guest
 
Posts: n/a
Default Petri Networks - dividers of N

How to make the dividers of N using Petri Networks. I mean, for
example: You put 6 at the begining of the network and you receive 2, 3,
6 as a result on the way out. I am using the Funsys software.
Any ideas?

Thank You

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Efficient clock dividers Rob Gaddi FPGA 2 11-14-2008 12:05 AM
Large unsigned dividers with limited clock cycles, how can I design it? Mr. Ken Verilog 2 09-11-2006 11:51 PM
cascaded dividers for dividing down clocks anand Verilog 1 08-16-2006 10:21 PM
flow based networks viji_sandy Verilog 0 10-28-2005 06:32 PM
flow based networks viji_sandy Verilog 0 10-28-2005 06:32 PM


All times are GMT +1. The time now is 01:50 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2012, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved