FPGA Central

Hi,

my poly is G(x)= 1 + x^39 + x^58
and my databuswith ist 64bit.

And that´s my implementation:
( scramble_1s is the history of the scrambler, data_0 the data input, and
scrambled_s is current scrambling result )

scramble: process(scrambled_s,data_0,scrambled1_s)
variable scrambled_v : std_logic_vector(63 downto 0);
begin
if CLK'event and CLK = '1' then
for i in 0 to 17 loop
scrambled_v(i) := scrambled_v(7+i) XOR scrambled_v(46+i) XOR data_0(i);
end loop;
for i in 18 to 56 loop
scrambled_v(i) := scrambled_v(7+i) XOR scrambled1_s(i-18) XOR data_0(i);
end loop;
for i in 57 to 63 loop
scrambled_v(i) := scrambled1_s(i-57) XOR scrambled1_s(i-18) XOR
data_0(i);
end loop;
scrambled_s <= scrambled_v;
end if;
end process scramble;

Something goes wrong here, don´t know what :-)

any suggestions?

thanks,
thomas

Problem solved!

I used a generic prbs generator!

now it works fine :-)

Thomas

"T. Irmen" <tirmen@gmx.net> schrieb im Newsbeitrag
news:bsrlq7$7du$1@online.de...
> Hi,
>
> my poly is G(x)= 1 + x^39 + x^58
> and my databuswith ist 64bit.
>
> And that´s my implementation:
> ( scramble_1s is the history of the scrambler, data_0 the data input, and
> scrambled_s is current scrambling result )
>
> scramble: process(scrambled_s,data_0,scrambled1_s)
> variable scrambled_v : std_logic_vector(63 downto 0);
> begin
> if CLK'event and CLK = '1' then
> for i in 0 to 17 loop
> scrambled_v(i) := scrambled_v(7+i) XOR scrambled_v(46+i) XOR data_0(i);
> end loop;
> for i in 18 to 56 loop
> scrambled_v(i) := scrambled_v(7+i) XOR scrambled1_s(i-18) XOR
data_0(i);
> end loop;
> for i in 57 to 63 loop
> scrambled_v(i) := scrambled1_s(i-57) XOR scrambled1_s(i-18) XOR
> data_0(i);
> end loop;
> scrambled_s <= scrambled_v;
> end if;
> end process scramble;
>
> Something goes wrong here, don´t know what :-)
>
> any suggestions?
>
> thanks,
> thomas
>
>

Hi,

Just wanted to show, how to do these LFSRs in somewhat more readable. I dont
remember what was the polynominal for the register below, but I think you
get the picture...

Regards and happy new year,
juza

process (CLK1, Reset)
begin
if Reset = '1' then
LFSR_1 <= S1;
elsif CLK1'event and CLK1 = '1' then
if ena_falling = '1' then
LFSR_1(0) <= LFSR_1(1) xor LFSR_1(2) xor LFSR_1(4) xor
LFSR_1(15);
LFSR_1(15 downto 1) <= LFSR_1(14 downto 0);
end if;
end if;
end process;

"T. Irmen" <tirmen@gmx.net> wrote in message news:bsrlq7$7du$1@online.de...
> Hi,
>
> my poly is G(x)= 1 + x^39 + x^58
> and my databuswith ist 64bit.
>
> And that´s my implementation:
> ( scramble_1s is the history of the scrambler, data_0 the data input, and
> scrambled_s is current scrambling result )
>
> scramble: process(scrambled_s,data_0,scrambled1_s)
> variable scrambled_v : std_logic_vector(63 downto 0);
> begin
> if CLK'event and CLK = '1' then
> for i in 0 to 17 loop
> scrambled_v(i) := scrambled_v(7+i) XOR scrambled_v(46+i) XOR data_0(i);
> end loop;
> for i in 18 to 56 loop
> scrambled_v(i) := scrambled_v(7+i) XOR scrambled1_s(i-18) XOR
data_0(i);
> end loop;
> for i in 57 to 63 loop
> scrambled_v(i) := scrambled1_s(i-57) XOR scrambled1_s(i-18) XOR
> data_0(i);
> end loop;
> scrambled_s <= scrambled_v;
> end if;
> end process scramble;
>
> Something goes wrong here, don´t know what :-)
>
> any suggestions?
>
> thanks,
> thomas
>
>

mmmh, thats a serial implementation and not readable also :-)

Happy new year!

Thomas


"jussi l" <jusa@removethis.ee.tut.fi> schrieb im Newsbeitrag
news:bstucl$1hn$1@news.cc.tut.fi...
> Hi,
>
> Just wanted to show, how to do these LFSRs in somewhat more readable. I
dont
> remember what was the polynominal for the register below, but I think you
> get the picture...
>
> Regards and happy new year,
> juza
>
> process (CLK1, Reset)
> begin
> if Reset = '1' then
> LFSR_1 <= S1;
> elsif CLK1'event and CLK1 = '1' then
> if ena_falling = '1' then
> LFSR_1(0) <= LFSR_1(1) xor LFSR_1(2) xor LFSR_1(4) xor
> LFSR_1(15);
> LFSR_1(15 downto 1) <= LFSR_1(14 downto 0);
> end if;
> end if;
> end process;
>
> "T. Irmen" <tirmen@gmx.net> wrote in message
news:bsrlq7$7du$1@online.de...
> > Hi,
> >
> > my poly is G(x)= 1 + x^39 + x^58
> > and my databuswith ist 64bit.
> >
> > And that´s my implementation:
> > ( scramble_1s is the history of the scrambler, data_0 the data input,
and
> > scrambled_s is current scrambling result )
> >
> > scramble: process(scrambled_s,data_0,scrambled1_s)
> > variable scrambled_v : std_logic_vector(63 downto 0);
> > begin
> > if CLK'event and CLK = '1' then
> > for i in 0 to 17 loop
> > scrambled_v(i) := scrambled_v(7+i) XOR scrambled_v(46+i) XOR
data_0(i);
> > end loop;
> > for i in 18 to 56 loop
> > scrambled_v(i) := scrambled_v(7+i) XOR scrambled1_s(i-18) XOR
> data_0(i);
> > end loop;
> > for i in 57 to 63 loop
> > scrambled_v(i) := scrambled1_s(i-57) XOR scrambled1_s(i-18) XOR
> > data_0(i);
> > end loop;
> > scrambled_s <= scrambled_v;
> > end if;
> > end process scramble;
> >
> > Something goes wrong here, don´t know what :-)
> >
> > any suggestions?
> >
> > thanks,
> > thomas
> >
> >
>
>