FPGA Central

Hi,
I am currently writing a test bench that contains a signal assignment within
a sequential process,

a<= b;

'a' is never assigned the value b during the run. I have several packages
included in this bench. I suspect operator overloading occuring. Can/does
Modelsim (the IDE I am using) have the capability to detect this is
happening? Or does anyone know a good way to trace or eliminate this
possibility?

Thanks

"JJ" <[email protected]> wrote in message
news:Owrzc.1519$[email protected] ...
> Hi,
> I am currently writing a test bench that contains a signal assignment
within
> a sequential process,
>
> a<= b;
>
> 'a' is never assigned the value b during the run. I have several packages
> included in this bench. I suspect operator overloading occuring. Can/does

The assignment operator can not be overloaded.

My first quess would be that signal a is untentionally multiple driven (from
different processes). Since you use ModelSim you can use the command:
drivers a <return>
to find the driver for signal a.

Egbert Molenkamp

"Egbert Molenkamp" <[email protected]> writes:

> "JJ" <[email protected]> wrote in message
> news:Owrzc.1519$[email protected] ...
> > Hi,
> > I am currently writing a test bench that contains a signal assignment
> within
> > a sequential process,
> >
> > a<= b;
> >
> > 'a' is never assigned the value b during the run. I have several packages
> > included in this bench. I suspect operator overloading occuring. Can/does
>
> The assignment operator can not be overloaded.
>
> My first quess would be that signal a is untentionally multiple driven (from
> different processes). Since you use ModelSim you can use the command:
> drivers a <return>
> to find the driver for signal a.
>
> Egbert Molenkamp

As usual, Egbert's advice is good, but I would also put a breakpoint at the
beginning of your sequential process and see if the process sensitivity list or
other IF/THEN code is not working the way you expect it to by single stepping
through the process.

Note too that a signal with no driver will be a 'U' but a signal with multiple
drivers will likely be an 'X'.

I ended up calling Modelsim - I had upgraded to 5.8c from 5.5(something),
the advice was "Always blow away your work directory and start again when
you upgrade" - Guess what? Worked like a charm...

I'm not going crazy after all!


"JJ" <[email protected]> wrote in message
news:Owrzc.1519$[email protected] ...
> Hi,
> I am currently writing a test bench that contains a signal assignment
within
> a sequential process,
>
> a<= b;
>
> 'a' is never assigned the value b during the run. I have several packages
> included in this bench. I suspect operator overloading occuring. Can/does
> Modelsim (the IDE I am using) have the capability to detect this is
> happening? Or does anyone know a good way to trace or eliminate this
> possibility?
>
> Thanks
>
>