FPGA Central

Hello All,
I was wondering whether there is a way to measure the simulation time
of an event in VHDL.

I am using modelsim simulator with the VHDL capabilites.

To put the same question other way, is there a $time equivalent of
verilog calls in VHDL?

Any answers would be greatly appreciated.

Regards
Hariharan K Srinivasan.

<[email protected]> wrote in message
news:[email protected] oups.com...
> Hello All,
> I was wondering whether there is a way to measure the simulation time
> of an event in VHDL.
>
> I am using modelsim simulator with the VHDL capabilites.
>
> To put the same question other way, is there a $time equivalent of
> verilog calls in VHDL?

The built-in VHDL function "now" (which takes no parameters) returns the
current simulation time. Is that what you're looking for?

Cheers,

-Ben-

On Mar 27, 2:35 pm, "Ben Jones" <ben.jo...@xilinx.com> wrote:
> <harisr...@gmail.com> wrote in message
>
> news:[email protected] oups.com...
>
> > Hello All,
> > I was wondering whether there is a way to measure the simulation time
> > of an event in VHDL.
>
> > I am using modelsim simulator with the VHDL capabilites.
>
> > To put the same question other way, is there a $time equivalent of
> > verilog calls in VHDL?
>
> The built-in VHDL function "now" (which takes no parameters) returns the
> current simulation time. Is that what you're looking for?
>
> Cheers,
>
> -Ben-

hello all.. please excuse me for my silly doubt..
im really new to VHDL. How do u find help for VHDL online...
Could anyone please tell me how to solve this problem ?

On Mar 31, 7:17 pm, "sathya" <sathyaj...@gmail.com> wrote:
> On Mar 27, 2:35 pm, "Ben Jones" <ben.jo...@xilinx.com> wrote:
>
>
>
> > <harisr...@gmail.com> wrote in message
>
> >news:[email protected] roups.com...
>
> > > Hello All,
> > > I was wondering whether there is a way to measure the simulation time
> > > of an event in VHDL.
>
> > > I am using modelsim simulator with the VHDL capabilites.
>
> > > To put the same question other way, is there a $time equivalent of
> > > verilog calls in VHDL?
>
> > The built-in VHDL function "now" (which takes no parameters) returns the
> > current simulation time. Is that what you're looking for?
>
> > Cheers,
>
> > -Ben-
>
> hello all.. please excuse me for my silly doubt..
> im really new to VHDL. How do u find help for VHDL online...
> Could anyone please tell me how to solve this problem ?

By using Google :-)

Also see: www.vhdl.org/comp.lang.vhdl

Regards
Ajeetha, CVC
www.noveldv.com

sathya wrote:

> im really new to VHDL. How do u find help for VHDL online...

Ask a question about VHDL.

-- Mike Treseler