FPGA Central

Hi,

How to print std_logic_vector variable into hex string in VHDL?

Thanks,

Carson

> How to print std_logic_vector variable into hex string in VHDL?
>

Forgotten the exact syntax & textbook not to hand, but something like:

use std.textio

and then use:

HWRITE (myline, signame);
WRITELINE (myfile, myline);
where signame is your std_log_vec.

Niv.

Carson wrote:

> How to print std_logic_vector variable into hex string in VHDL?

Here's one way:
http://home.comcast.net/~mike_treseler/print_vec.vhd

-- Mike Treseler

Thanks,

Is there any command like "report integer'image(myvalue)"; so that it
will print out hex?

Mike Treseler wrote:
> Carson wrote:
>
>> How to print std_logic_vector variable into hex string in VHDL?
>
>
> Here's one way:
> http://home.comcast.net/~mike_treseler/print_vec.vhd

Here's another:

http://www.eda.org/vhdl-200x/vhdl-20..._additions.vhd

The function is called "to_hstring", it works like this:

report "The string was " & to_hstring (slvec)

There is also a "to_string" and "to_ostring" function in this package,
which containts all of the additions we plan to make to std_logic_1164
in VHDL-2006.