FPGA Central

How should I make my program more effective....?

Can anyone tell the modification for the program which does the memory
controller operation...


Please tell me the modification for the program....


entity mc is
port(
wrcut bit_vector(2 downto 0);
clk,rw: in bit;
ea:in bit_vector(3 downto 0)
);
end mc;

architecture behave of mc is
begin
process(clk)
variable sar1:bit_vector(7 downto 0);variable rar1:bit_vector(7 downto
0);variable car1:bit_vector(7 downto 0);
variable sar2:bit_vector(7 downto 0);variable rar2:bit_vector(7 downto
0);variable car2:bit_vector(7 downto 0);
variable sar3:bit_vector(7 downto 0);variable rar3:bit_vector(7 downto
0);variable car3:bit_vector(7 downto 0);
variable temp:bit_vector(3 downto 0);
variable l1,l2,l3:bit_vector(1 downto 0);
begin
if(clk='1')then
sar1 := "10001000";
sar2 := "10101010";
sar3 := "10111010";
rar1 := "10011000";
rar2 := "10001100";
rar3 := "11101000";
car1 := "10111011";
car2 := "10001111";
car3 := "11111000";

temp := sar1(3 downto 0);
if (ea = temp) then
wrc(0) <= 1;
l1 := 1;
else
wrc(0) <= 0;
end if;

temp := sar2(3 downto 0);
if (ea = temp) then
wrc(0) <= 1;
l1 := 2;
else
wrc(0) <= 0;
end if;

temp := sar3(3 downto 0);
if (ea = temp) then
wrc(0) <= 1;
l1 := 3;
else
wrc(0) <= 0;
end if;

temp := rar1(3 downto 0);
if (ea = temp) then
wrc(1) <= 1;
l2 := 1;
else
wrc(1) <= 0;
end if;

temp := rar2(3 downto 0);
if (ea = temp) then
wrc(1) <= 1;
l2 := 1;
else
wrc(1) <= 0;
end if;

temp := rar3(3 downto 0);
if (ea = temp) then
wrc(1) <= 1;
l2 := 1;
else
wrc(1) <= 0;
end if;

temp := car1(3 downto 0);
if (ea = temp) then
wrc(2) <= 1;
l3 := 1;
else
wrc(2) <= 0;
end if;

temp := car2(3 downto 0);
if (ea = temp) then
wrc(2) <= 1;
l3 := 1;
else
wrc(2) <= 0;
end if;

temp := car3(3 downto 0);
if (ea = temp) then
wrc(2) <= 1;
l3 := 1;
else
wrc(2) <= 0;
end if;

if(rw = '0')then -- for readers
if (wrc = "000") then --rcw = 000, Put in rar
rar2(3 downto 0) := ea;
elsif (wrc = "100") then --rcw = 001
rar2(3 downto 0) := ea;
elsif (wrc = "001") then --rcw = 010, RAW, enter in rar and link with
matched sar
rar2(3 downto 0) := ea;
if(l1 = 1)then
rar2(5 downto 4) := "00";
elsif(l1 = 2)then
rar2(5 downto 4) := "01";
elsif(l1 = 3)then
rar2(5 downto 4) := "10";
end if;
elsif (wrc = "101") then --rcw = 011, enter in rar and link with sar
rar2(3 downto 0) := ea;
if(l1 = 1)then
rar2(5 downto 4) := "00";
elsif(l1 = 2)then
rar2(5 downto 4) := "01";
elsif(l1 = 3)then
rar2(5 downto 4) := "10";
end if;
elsif(wrc = "010")then --rcw = 100, enter in rar, link for service
with matched rar.
rar3(3 downto 0) := ea;
if(l1 = 1)then
rar3(5 downto 4) := "00";
elsif(l1 = 2)then
rar3(5 downto 4) := "01";
elsif(l1 = 3)then
rar3(5 downto 4) := "10";
end if;
elsif(wrc = "110")then --rcw = 101, enter in rar with link to match
rar.
rar3(3 downto 0) := ea;
if(l2 = 1)then
rar3(5 downto 4) := "00";
elsif(l2 = 2)then
rar3(5 downto 4) := "01";
elsif(l2 = 3)then
rar3(5 downto 4) := "10";
end if;
elsif(wrc = "011")then --rcw = 110, RAW, enter in rar link with
matched sar.
rar2(3 downto 0) := ea;
if(l1 = 1)then
rar2(5 downto 4) := "00";
elsif(l1 = 2)then
rar2(5 downto 4) := "01";
elsif(l1 = 3)then
rar2(5 downto 4) := "10";
end if;
end if;

elsif(rw='1')then -- for writers.
if(wrc = "000")then --rwc = 000, no hazard, enter in sar
sar2(3 downto 0) := ea;
elsif(wrc = "100")then --rcw = 001, enter in sar
sar2(3 downto 0) := ea;
elsif(wrc = "001")then --rcw = 010, enter in sar
sar2(3 downto 0) := ea;
elsif(wrc = "101") then --rcw = 011, ener in sar and link with sar
sar2(3 downto 0) := ea;
if(l1 = 1)then
sar2(5 downto 4) := "00";
elsif(l1 = 1)then
sar2(5 downto 4) := "01";
elsif(l1 = 1)then
sar2(5 downto 4) := "10";
end if;
elsif(wrc = "010")then --rcw = 100, WAR, enter in sar, link with
rar.
sar2(3 downto 0) := ea;
if(l2 = 1)then
sar2(5 downto 4) := "00";
elsif(l2 = 1)then
sar2(5 downto 4) := "01";
elsif(l2 = 1)then
sar2(5 downto 4) := "10";
end if;
elsif(wrc = "110")then --rcw = 101, WAR, enter in sar link with rar.
sar2(3 downto 0) := ea;
if(l2 = 1)then
sar2(5 downto 4) := "00";
elsif(l2 = 1)then
sar2(5 downto 4) := "01";
elsif(l2 = 1)then
sar2(5 downto 4) := "10";
end if;
end if;
end if; --rw
end if; --clk
end process;
end behave;




Please tell me how can I modify and write in less numnber of lines,,,


Waiting

Kumar wrote:

> Please tell me how can I modify and write in less numnber of lines,,,

Code and babies are born ugly.
However, it is a good idea to make sure
the baby can cry before you clean him up much.
In vhdl you do this by running a sim to make sure
the design does what you expect.
If it doesn't, clean-up is irrelevant.

Once your code sims ok, I would start by
putting repeated code sequences into loops.
Re-run your sim after each clean up.

-- Mike Treseler

Ya baby need to be cleaned but which part of th e baby!! Can u tell
me exact changed code???

Kumar wrote:
> Can u tell me exact changed code???

Post a working testbench and I'll have a look.

-- Mike Treseler

Mike Treseler wrote:

> Code and babies are born ugly. However, it is a good idea to make
> sure the baby can cry before you clean him up much. In vhdl you do
> this by running a sim to make sure the design does what you expect.
> If it doesn't, clean-up is irrelevant.

IMHO, it depends...

*Really* ugly code that is a result of poor design due to, for example,
inexperience may be a 'lost cause' if one wastes too much time trying to
get it to work. At some point down this track one generally questions
oneself whether or not there is a better way to do things, and by asking
for advice/pointers you generally end up saving time and learning
something along the way.

I'm NOT saying that this post is an example of that!

Just saying that *some* paths are best abandoned.

Regards,
Mark

Here is testbench Mike!!!

logfile mem.log

bitvec input ea_3 ea_2 ea_1 ea_0
bitvec f rw
sbvec input 1000
sbvec f 0

watch clk
dl
uvec clk 10101010101010101010
watch wrc_2
watch wrc_1
watch wrc_0
runvec

sbvec input 1010
sbvec f 0

watch clk
dl
uvec clk 10101010101010101010
watch wrc_2
watch wrc_1
watch wrc_0
runvec