FPGA Central

Hello everybody,

I want to use the signal defined in one architecture in VHDL to
another architecture. I have two architecture in the same .vhd file
and I am using Component mapping. I required the result of calculation
of a signal to be used in second architecture. Can any one tell how to
defined signal so that it is globally visible to other architectures.

Regards

Khan

Muhammad Khan wrote:

> I want to use the signal defined in one architecture in VHDL to
> another architecture. I have two architecture in the same .vhd file
> and I am using Component mapping. I required the result of calculation
> of a signal to be used in second architecture. Can any one tell how to
> defined signal so that it is globally visible to other architectures.

Hello Muhammad,

this is a common question.

The clean way for handling this is to feed the signal through
the port maps.

Regards,
Mario

--
----------------------------------------------------------------------
Digital Force / Mario Trams [email protected]
[email protected]
Chemnitz University of Technology http://www.tu-chemnitz.de/~mtr
Dept. of Computer Science Tel.: (+49) 371 531 1660
Chair of Computer Architecture Fax.: (+49) 371 531 1818
----------------------------------------------------------------------

Hi Khan,
If you declare a signal in a package and you include the package
then the signal can be globally used by all architectures that
reference that package. This is for simulation only and will not
work for synthesis.

Jon


[email protected] (Muhammad Khan) wrote in message news:<[email protected] com>...
> Hello everybody,
>
> I want to use the signal defined in one architecture in VHDL to
> another architecture. I have two architecture in the same .vhd file
> and I am using Component mapping. I required the result of calculation
> of a signal to be used in second architecture. Can any one tell how to
> defined signal so that it is globally visible to other architectures.
>
> Regards
>
> Khan

Jon wrote:

> Hi Khan,
> If you declare a signal in a package and you include the package
> then the signal can be globally used by all architectures that
> reference that package. This is for simulation only and will not
> work for synthesis.


This will work for synthesis in Synplify Pro 7.3.


>
> Jon
>
>
> [email protected] (Muhammad Khan) wrote in message news:<[email protected] com>...
>
>>Hello everybody,
>>
>>I want to use the signal defined in one architecture in VHDL to
>>another architecture. I have two architecture in the same .vhd file
>>and I am using Component mapping. I required the result of calculation
>>of a signal to be used in second architecture. Can any one tell how to
>>defined signal so that it is globally visible to other architectures.
>>
>>Regards
>>
>>Khan
>>

Ken McElvain wrote:

> Jon wrote:

>> If you declare a signal in a package and you include the package
>> then the signal can be globally used by all architectures that
>> reference that package. This is for simulation only and will not
>> work for synthesis.
>
> This will work for synthesis in Synplify Pro 7.3.

Cool. Never seen that in synthesis before.
How did you get test cases?

-- Mike Treseler