FPGA Central

I'm wondering if anyone knows of a tool that will take a synthesized
netlist (or individual unit VHDL files), and analyze the logic to
report possible vectors that will cause a glitch to occur. I can then
analyze these and determine if these vectors are possible and if they
need to be fixed.

I realize I can get this information by looking at simulation waves,
however, I can't exactly do this for the entire design and only a
small number of possible input vector combinations are tested.

If there's another group that might be better ask this question in,
let me know.

Thanks,
baver

Hi,

> I'm wondering if anyone knows of a tool that will take a synthesized
> netlist (or individual unit VHDL files), and analyze the logic to
> report possible vectors that will cause a glitch to occur. I can then
> analyze these and determine if these vectors are possible and if
> they need to be fixed.

A tool that can do structural analysis on your code/netliste might fit
the job. Since glitches aren't bad per default, you could derive rules
that describe "faulty" circuit structures and feed these into an HDL
linter like Spyglass or others.

Arnim

baver wrote:
> I'm wondering if anyone knows of a tool that will take a synthesized
> netlist (or individual unit VHDL files), and analyze the logic to
> report possible vectors that will cause a glitch to occur.

For a synchronous design, static timing analysis
does that job for any possible input vector,
without requiring simulation.

So step one is, make the design synchronous.

-- Mike Treseler

On 23 Dez., 01:26, baver <richard.baverst...@gmail.com> wrote:
> I'm wondering if anyone knows of a tool that will take a synthesized
> netlist (or individual unit VHDL files), and analyze the logic to
> report possible vectors that will cause a glitch to occur. I can then

What do you call a glitch? A change from a start value to its oposite
value and back to start value in small amount of time compared to your
clock? Only simulation glitches within the same simulation time but
different ticks?
In normal designs this tool would report enormous amount of patterns,
as a netlist usual contains many glitches.

Glitches should be handled by design in my opinion (eg. registered
outputs), not by analysis. This means your design has to be designed
in a way, that it overcomes all glitch effects even on clock and
reset. You should be aware, that glitches in netlists come due to
assumed timings, which are not guaranteed in reality.
You might see complete different glitches for best, worst and typical
timing but your real silicon will behave somewhere between worst and
best. And a glitch behavior on typical timing has no _necessary_ link
to the silicon you solder on the pcb.

bye Thomas