FPGA Central

Hi,

I have a dual port BRAM, accessible from the PPC of a virtex.

I was looking for some VHDL to take the contents of an address from the
other port (port B) , decrement the content , then stick it back into the
same address , word, byte ,long word, it does not matter., via port B.

I know it sounds like a stupid waste of time, but specifically I need
something to test the PPC and data paths , because something is corrupting
someplace, (data or timing), i need to track it down)


I've had a look around , but good examples seem to be in short supply.
Can anyone offer some pointers to examples.

The other question that is confusing me about Xilinx, If I try and take a
dual port memory and set port A to an XPS_BRAM_controller at one address,
then set port B to another XPS_BRAM_controller at a second address (to
build a loop back test at two different addresses) Xilinx tools will not
allow it?


Steve

On Tue, 7 Jul 2009 19:12:59 +0800, steve <[email protected]> wrote:

>I have a dual port BRAM, accessible from the PPC of a virtex.
>
>I was looking for some VHDL to take the contents of an address from the
>other port (port B) , decrement the content , then stick it back into the
>same address , word, byte ,long word, it does not matter., via port B.

It's easy provided nothing else needs to access port B.
How do you plan to specify the address? Is there a
register, writeable by the CPU? Or do you intend to
hard-code the port B address, just as a test? Do you
want the decrement to run continuously, as some sort
of timed downcounter; or do you want it to be one-shot,
triggered by some write to a peripheral by the PPC?

>I've had a look around , but good examples seem to be in short supply.
>Can anyone offer some pointers to examples.

The read/decr/write thing is surely just a fairly simple state
machine and a decrementer; I'm not too surprised there are
few examples, but it should be easy to throw one together
along these lines:

State 0: waiting for the start signal. On start, go to...
State 1: drive address on to BRAM, enable read, go to...
State 2: capture data into a register that feeds a decrementer
whose output goes to the write data port. Go to:
State 3: do nothing, just give the decr time to settle. Go to...
State 4: assert write-enable (address is still OK from state 1).
Go to state 0 and wait for the next start command.


>The other question that is confusing me about Xilinx, If I try and take a
>dual port memory and set port A to an XPS_BRAM_controller at one address,
>then set port B to another XPS_BRAM_controller at a second address (to
>build a loop back test at two different addresses) Xilinx tools will not
>allow it?

Never used the XPS_BRAM_... macros; I guess others here have, though.
--
Jonathan Bromley, Consultant

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>
>Steve
>
>
>