FPGA Central

I have a bunch of 32 bit registers in my design, where bit slices aren't
being taken.

It would be nice if the registers could be declared with just a size spec
like

reg [32] my_reg;

rather than

reg [31:0] my_reg;


Rob

Robert Finch wrote:

> I have a bunch of 32 bit registers in my design, where bit slices aren't
> being taken.
>
> It would be nice if the registers could be declared with just a size spec
> like
>
> reg [32] my_reg;
>
> rather than
>
> reg [31:0] my_reg;
>
>
> Rob

I see four possibilities:
reg [32:1] my_reg;
reg [31:0] my_reg;
reg [1:32] my_reg;
reg [0:31] my_reg;

I wish they'd keep it [a:b]

Robert Finch wrote:

> I have a bunch of 32 bit registers in my design, where bit slices
> aren't being taken.
> It would be nice if the registers could be declared with just a size
> spec like
> reg [32] my_reg;

`define MY_REGISTER_RANGE 31:0

reg [`MY_REGISTER_RANGE] myRegister;

Regards,
Mark

SystemVerilog has a number of ways to do this:

you CAN specify an array in SV with just a size, but that only works
for unpacked arrays (i.e. memories), so you can do:

reg [31:0] mem [1024];

however, you can declare user defined types, so:

typedef reg [31:0] rob_t;

rob_t my_reg;