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12-12-2006, 08:20 PM
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VHDL 2 VERILOG CONVERTER FOR AHB
Hi
Any one has vhdl to verilog converter ????? i have one but it translates only 60 lines of code. if you have and if u cannot pass on to me, could you please conver the ahb generator in opencores to verilog format and post it ???? as i see there are many questions about ahb models there is one is opencores but in vhdl, conversion it to verilog would be greatly appreciated. Regards 
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12-13-2006, 01:20 AM
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Re: VHDL 2 VERILOG CONVERTER FOR AHB
"Terabits", May I ask you which HDL simulator you are using? Utku. terabits wrote: > Hi > > Any one has vhdl to verilog converter ????? > i have one but it translates only 60 lines of code. > if you have and if u cannot pass on to me, could you please conver the > ahb generator in opencores to verilog format and post it ???? > as i see there are many questions about ahb models there is one is > opencores but in vhdl, conversion it to verilog would be greatly > appreciated. > > Regards
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12-13-2006, 01:37 AM
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Re: VHDL 2 VERILOG CONVERTER FOR AHB
Modelsim, I know it supports mixed language simulations but i donno
VHDL  On Dec 12, 4:20 pm, "Utku Özcan" <utku.oz...@gmail.com> wrote: > "Terabits", May I ask you which HDL simulator you are using? > > Utku. > > terabits wrote: > > Hi > > > Any one has vhdl to verilog converter ????? > > i have one but it translates only 60 lines of code. > > if you have and if u cannot pass on to me, could you please conver the > > ahb generator in opencores to verilog format and post it ???? > > as i see there are many questions about ahb models there is one is > > opencores but in vhdl, conversion it to verilog would be greatly > > appreciated. > > > Regards
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12-15-2006, 09:45 PM
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Re: VHDL 2 VERILOG CONVERTER FOR AHB
Hi terabits,
General conversion of VHDL to Verilog or visa versa is totally non-trivial. I doubt that there is any serious professional solution out there that can deal with all the details of each language. However, ModelSim supports mixed VHDL and Verilog simulation. Also most other EDA tools support mixed language compilation, so you would not need to translate one to the other. Rob "terabits" <[email protected]> wrote in message news:[email protected] ups.com... Modelsim, I know it supports mixed language simulations but i donno VHDL On Dec 12, 4:20 pm, "Utku Özcan" <utku.oz...@gmail.com> wrote: > "Terabits", May I ask you which HDL simulator you are using? > > Utku. > > terabits wrote: > > Hi > > > Any one has vhdl to verilog converter ????? > > i have one but it translates only 60 lines of code. > > if you have and if u cannot pass on to me, could you please conver the > > ahb generator in opencores to verilog format and post it ???? > > as i see there are many questions about ahb models there is one is > > opencores but in vhdl, conversion it to verilog would be greatly > > appreciated. > > > Regards
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