FPGA Central

Hi,

Can anyone give an easy-to-understand explanation of the "->" operator?
I looked many places but it was not well documented. Please give
examples if possible. Thanks lot.

Jason Zheng <[email protected]> wrote in message news:<cd9s69$3ic$[email protected]>...
> Hi,
>
> Can anyone give an easy-to-understand explanation of the "->" operator?
> I looked many places but it was not well documented. Please give
> examples if possible. Thanks lot.

See page 139 of the Verilog IEEE Std 1364-2001 Specification.

Jeremy

It is used for *simulation* purposes to trigger event.
It is used with a "@" construct that is waiting for the
event. A simple example:

event err;

always @(err)
begin
$display("I got an error");
// maybe do more reporting or dumping here...
....
// maybe you want to do a $finish if batch mode, or
// something other than a $stop.
$stop;
end

// deep inside your code....
if (expect !== actual)
// I see an error, trigger the handler.
-> err;

NOTE: no posedge or negedge, an event simply happens.

I wouldn't use this in code to be synthesized.

I hope this helps.

John P


Jason Zheng <[email protected]> wrote in message news:<cd9s69$3ic$[email protected]>...
> Hi,
>
> Can anyone give an easy-to-understand explanation of the "->" operator?
> I looked many places but it was not well documented. Please give
> examples if possible. Thanks lot.